Abstract: A first-in-first-out memory device which is operable at a high-speed is disclosed. The memory device comprises a plural stages of memory units and a plural stages of control unit, each of the control units including a circuit for indicating whether its stage holds effective data or not, a circuit for receiving a signal of the indicating means of the previous stage, and a circuit generating a write signal when the memory cell holds no effective data and the previous stage hold effective data, in which the write signal is used to remove data stored in the previous memory cell to the corresponding stage memory cell.

Abstract: A plurality of information handling units communicate asynchronously via a common bus using a single signal line. Each information handling unit includes a self-control type bus utilization unit connected to the signal line and operative to connect the common bus to an internal bus of the information handling unit. This unit includes an own name address generator responsive to a bus request signal for outputting the address of the information handling unit, the address being encoded according to that information handling unit's priority among the plurality of information handling units. Transmission gates couple the address to the common bus, and a decision unit compares a signal on the common bus and the address to make a decision based on the assigned priority of the information handling unit to derive a bus grant signal. This signal and a bus available signal on the single signal line are used to derive a signal to drive transmission gates that couple the common bus to the internal bus.