Patents by Inventor Toshio Arakawa
Toshio Arakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150347644Abstract: A designing apparatus generates a logic cone and calculates an area ratio between a first triangle and a second triangle. The first triangle has a logic cell as an angle in an m-th stage between input and output stages and input-side FFs as the other angles at both ends of the input stage, the FFs connected to input of the cell. The second triangle has an output-side FF as an angle in the output stage and logic cells as the other angles at both ends of the m-th stage, the cells connected to input of the FF in the output stage. The apparatus sets, when the ratio matches a predetermined ratio, a first logic cone block between the input and m-th stages and a second logic cone block between the output and m-th stages as logic synthesis units and performs logic synthesis by using the logic synthesis units.Type: ApplicationFiled: May 26, 2015Publication date: December 3, 2015Inventors: Toshio ARAKAWA, Yoshinori Yamagata
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Publication number: 20060053399Abstract: A designing device for designing a layout of a semiconductor device includes a layout position candidate extracting unit for obtaining layout position candidates of a regulator, a tentatively wiring unit for tentatively arranging the regulator at the layout position candidates and tentatively laying out a power line, and a regulator layout position deciding unit for deciding a position of a tentative layout at which an area of the power line that is tentatively laid out is the smallest as the layout position of the regulator.Type: ApplicationFiled: December 20, 2004Publication date: March 9, 2006Applicant: Fujitsu LimitedInventors: Hiroyuki Honda, Toshio Arakawa, Hiroshi Mawatari, Norito Hibino, Kouji Arai, Keigo Tada, Fukuji Kihara
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Patent number: 6990642Abstract: The present invention provides a method for designing LSI including a logic circuit equipped with a scan circuit without generating a hard-macro library for the scan flip flops constituting the scan circuit. According to the method, first netlist NL1 is converted into second netlist NL2 by adding scan circuit including scan flip-flops. Order data for connecting scan chain of the scan circuit is extracted from the second netlist NL2. Such second netlist NL2 is converted into third netlist NL3 including only hard-macros, and the third netlist NL3 is laid-out by re-ordering the scan chain so that the newly generated order data for is stored temporally. Fourth netlist NL4 including scan circuit formed by scan flip-flops of soft-macros is generated on the basis of the stored order data, then the fourth netlist NL4 is converted into fifth netlist NL5 by substituting the scan flip-flops of soft-macros for standard cells of hard-macros.Type: GrantFiled: August 6, 2003Date of Patent: January 24, 2006Assignee: Fujitsu LimitedInventor: Toshio Arakawa
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Patent number: 6857107Abstract: In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing conditions, and, once a timing optimization processing is performed so that a plurality of cells are arranged on a chip, global wiring processing is implemented and the wiring congestion rate is analyzed. In addition, in small regions where a wiring congestion rate is so high that detailed wiring processing is judged to be difficult, cell rearrangement processing is implemented. Next, detailed wiring processing is performed with respect to the cells which have been rearranged. The rearrangement of cells is performed only in small regions with a high congestion rate, with the result that the overall cell arrangement in which timing is optimized is not changed markedly, whereby it is possible to reduce the probability of wiring being impossible in the course of the detailed wiring processing.Type: GrantFiled: February 22, 2002Date of Patent: February 15, 2005Assignee: Fujitsu LimitedInventors: Mitsuaki Nagasaka, Daisuke Miura, Masayuki Okamoto, Hiroyuki Honda, Toshio Arakawa, Shuji Yoshida, Kenji Yoshida, Kenji Kobayashi
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Patent number: 6781412Abstract: Each binary carry logic circuit 20 of half adder circuits other than that for the least significant digit comprises a transfer gate 212 turned on when an input bit A2 is active and receiving a carry-in bit *C2 at its data input, and a transistor 23, turned on when the input bit A2 is inactive, connected between a power supply potential VDD and the data output of the transfer gate 212 a signal on which is a carry-out bit *C3. Transfer gates 212 to 214 of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A2 to A4, letting the carry-in bit *C2 from the least significant digit propagate through the transfer gate chain at a high speed.Type: GrantFiled: February 13, 2002Date of Patent: August 24, 2004Assignee: Fujitsu LimitedInventors: Shuji Yoshida, Daisuke Miura, Toshio Arakawa, Mitsuaki Nagasaka, Kenji Yoshida, Hiroyuki Honda, Kenji Kobayashi, Masayuki Okamoto
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Patent number: 6760897Abstract: Disclosed is a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other. The method comprises the steps of (S2) sorting the terminals according to the width thereof; and (S3˜S11) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal.Type: GrantFiled: August 2, 2002Date of Patent: July 6, 2004Assignee: Fujitsu LimitedInventors: Toshio Arakawa, Daisuke Miura, Masayuki Okamoto, Mitsuaki Nagasaka, Hiroyuki Honda, Shuji Yoshida, Kenji Kobayashi, Kenji Yoshida
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Publication number: 20040040006Abstract: The present invention provides a method for designing LSI including a logic circuit equipped with a scan circuit without generating a hard-macro library for the scan flip flops constituting the scan circuit. According to the method, first netlist NL1 is converted into second netlist NL2 by adding scan circuit including scan flip-flops. Order data for connecting scan chain of the scan circuit is extracted from the second netlist NL2. Such second netlist NL2 is converted into third netlist NL3 including only hard-macros, and the third netlist NL3 is laid-out by re-ordering the scan chain so that the newly generated order data for is stored temporally. Fourth netlist NL4 including scan circuit formed by scan flip-flops of soft-macros is generated on the basis of the stored order data, then the fourth netlist NL4 is converted into fifth netlist NL5 by substituting the scan flip-flops of soft-macros for standard cells of hard-macros.Type: ApplicationFiled: August 6, 2003Publication date: February 26, 2004Applicant: FUJITSU LIMITEDInventor: Toshio Arakawa
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Publication number: 20030054619Abstract: Disclosed is a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other. The method comprises the steps of (S2) sorting the terminals according to the width thereof; and (S3˜S11) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal.Type: ApplicationFiled: August 2, 2002Publication date: March 20, 2003Applicant: Fujitsu LimitedInventors: Toshio Arakawa, Daisuke Miura, Masayuki Okamoto, Mitsuaki Nagasaka, Hiroyuki Honda, Shuji Yoshida, Kenji Kobayashi, Kenji Yoshida
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Publication number: 20030023938Abstract: In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing conditions, and, once a timing optimization processing is performed so that a plurality of cells are arranged on a chip, global wiring processing is implemented and the wiring congestion rate is analyzed. In addition, in small regions where a wiring congestion rate is so high that detailed wiring processing is judged to be difficult, cell rearrangement processing is implemented. Next, detailed wiring processing is performed with respect to the cells which have been rearranged. The rearrangement of cells is performed only in small regions with a high congestion rate, with the result that the overall cell arrangement in which timing is optimized is not changed markedly, whereby it is possible to reduce the probability of wiring being impossible in the course of the detailed wiring processing.Type: ApplicationFiled: February 22, 2002Publication date: January 30, 2003Applicant: Fujitsu LimitedInventors: Mitsuaki Nagasaka, Daisuke Miura, Masayuki Okamoto, Hiroyuki Honda, Toshio Arakawa, Shuji Yoshida, Kenji Yoshida, Kenji Kobayashi
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Publication number: 20020188641Abstract: Each binary carry logic circuit 20 of half adder circuits other than that for the least significant digit comprises a transfer gate 212 turned on when an input bit A2 is active and receiving a carry-in bit *C2 at its data input, and a transistor 23, turned on when the input bit A2 is inactive, connected between a power supply potential VDD and the data output of the transfer gate 212 a signal on which is a carry-out bit *C3. Transfer gates 212 to 214 of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A2 to A4, letting the carry-in bit *C2 from the least significant digit propagate through the transfer gate chain at a high speed.Type: ApplicationFiled: February 13, 2002Publication date: December 12, 2002Applicant: FUJITSU LIMITEDInventors: Shuji Yoshida, Daisuke Miura, Toshio Arakawa, Mitsuaki Nagasaka, Kenji Yoshida, Hiroyuki Honda, Kenji Kobayashi, Masayuki Okamoto
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Publication number: 20020047789Abstract: A method of designing a semiconductor integrated circuit includes the steps of generating a cell that includes a flip-flop and backup transistors, designing a circuit by use of the cell, and adjusting a timing by connecting the backup transistors to the flip-flop if there is a need to adjust timing of the flip-flop.Type: ApplicationFiled: February 21, 2001Publication date: April 25, 2002Inventors: Yasuhiko Inada, Daisuke Miura, Masayuki Okamoto, Mitsuaki Nagasaka, Toshio Arakawa
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Patent number: 5166486Abstract: A microwave oven includes a casing defining a heating chamber, a track member disposed in the heating chamber and having an undulate surface circumferentially extended, an electric motor mounted in the casing, a plurality of rolling members each moved along the undulate surface of the track member by the motor, rolling about respective axes thereof in contact with the undulate surface of the track member, and a turntable on which food to be cooked is placed, the turntable having a traveling face and placed on the rolling members so that the traveling face thereof is in contact with the rolling members, whereby the turntable is rotated with a vertical movement.Type: GrantFiled: October 10, 1990Date of Patent: November 24, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Morimasa Komatsu, Toshio Arakawa, Keizo Shimeno