Patents by Inventor Toshio Baba

Toshio Baba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8936962
    Abstract: An optical modulator according to the present invention is configured at least by a semiconductor layer subjected to a doping process so as to exhibit a first conductivity type, and a semiconductor layer subjected to a doping process so as to exhibit a second conductivity type. Further, in the optical modulator, at least the first conductivity type semiconductor layer, a dielectric layer, the second conductivity type semiconductor layer, and a transparent electrode optically transparent in at least a near-infrared wavelength region are laminated in order.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: January 20, 2015
    Assignee: NEC Corporation
    Inventors: Junichi Fujikata, Toshio Baba, Jun Ushida
  • Publication number: 20120003767
    Abstract: An optical modulator according to the present invention is configured at least by a semiconductor layer subjected to a doping process so as to exhibit a first conductivity type, and a semiconductor layer subjected to a doping process so as to exhibit a second conductivity type. Further, in the optical modulator, at least the first conductivity type semiconductor layer, a dielectric layer, the second conductivity type semiconductor layer, and a transparent electrode optically transparent in at least a near-infrared wavelength region are laminated in order.
    Type: Application
    Filed: February 15, 2010
    Publication date: January 5, 2012
    Applicant: NEC CORPORATION
    Inventors: Junichi Fujikata, Toshio Baba, Jun Ushida
  • Publication number: 20110176762
    Abstract: An optical modulator is formed with at least a portion of a semiconductor layer (8) that has undergone a doping process to exhibit a first conductivity and at least a portion of a semiconductor layer (9) that has undergone a doping process to exhibit a second conductivity overlapping with a dielectric layer (11) interposed. The surface of the semiconductor layer (8) of first conductivity has an uneven form in the portion in which the semiconductor layer (8) that exhibits first conductivity and the semiconductor layer (9) that exhibits second conductivity overlap with the dielectric layer (11) interposed. The dielectric layer (11) is formed on the semiconductor layer (8) of first conductivity that has the uneven form, and the semiconductor layer (9) of second conductivity is formed on the dielectric layer (11).
    Type: Application
    Filed: November 10, 2009
    Publication date: July 21, 2011
    Inventors: Junichi Fujikata, Toshio Baba, Jun Ushida
  • Patent number: 7883911
    Abstract: A Schottky photodiode includes a semiconductor layer and a conductive film provided in contact with the semiconductor layer. The conductive film has an aperture and a periodic structure provided around said aperture for producing a resonant state by an excited surface plasmon in a film surface of the conductive film by means of the incident light to the film surface. The photodiode detects near-field light that is generated by at the interface between the conductive film and semiconductor layer the excited surface plasmon. The aperture has a diameter smaller than the wavelength of the incident light.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: February 8, 2011
    Assignee: NEC Corporation
    Inventors: Keishi Oohashi, Tsutomu Ishi, Toshio Baba, Junichi Fujikata, Kikuo Makita
  • Patent number: 7728366
    Abstract: A Schottky photodiode includes a semiconductor layer and a conductive film provided in contact with the semiconductor layer. The conductive film has an aperture and a periodic structure provided around said aperture for producing a resonant state by an excited surface plasmon in a film surface of the conductive film by means of the incident light to the film surface. The photodiode detects near-field light that is generated by at the interface between the conductive film and semiconductor layer the excited surface plasmon. The aperture has a diameter smaller than the wavelength of the incident light.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: June 1, 2010
    Assignee: NEC Corporation
    Inventors: Keishi Oohashi, Tsutomu Ishi, Toshio Baba, Junichi Fujikata, Kikuo Makita
  • Publication number: 20090181535
    Abstract: Scale down design has posed problems in an increase in the resistance value of an interconnection structure and a decrease in the resistance to electromigration and stress migration. The present invention provides an interconnection structure of a high-reliability semiconductor device which has a low resistance value even in the case of scale down design and does not produce electromigration or stress migration, and a method of manufacturing the interconnection structure. Provided are a semiconductor device which has an interconnection or a connection plug, both of which are fabricated from a mixture of a metal and carbon nanotubes, in an interconnection trench or a via hole, both of which are formed on an insulating film on a substrate on which a semiconductor device element is formed, and a method of manufacturing this semiconductor device.
    Type: Application
    Filed: March 18, 2009
    Publication date: July 16, 2009
    Applicant: NEC CORPORATION
    Inventors: Toshitsugu SAKAMOTO, Hisao Kawaura, Toshio Baba, Fumiyuki Nihey, Yukinori Ochiai, Hiroo Hongo
  • Publication number: 20090176327
    Abstract: A Schottky photodiode includes a semiconductor layer and a conductive film provided in contact with the semiconductor layer. The conductive film has an aperture and a periodic structure provided around said aperture for producing a resonant state by an excited surface plasmon in a film surface of the conductive film by means of the incident light to the film surface. The photodiode detects near-field light that is generated by at the interface between the conductive film and semiconductor layer the excited surface plasmon. The aperture has a diameter smaller than the wavelength of the incident light.
    Type: Application
    Filed: March 11, 2009
    Publication date: July 9, 2009
    Inventors: Keishi Oohashi, Tsutomu Ishi, Toshio Baba, Junichi Fujikata, Kikuo Makita
  • Patent number: 7518247
    Abstract: There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron migration and stress migration, and having a high reliability and a method for manufacturing the same. A semiconductor device having a wiring or a connection plug made of a mixture of a metal and carbon nanotubes berried in a wiring groove or a via hole made in an insulating film on a substrate where a semiconductor chip is fabricated, and its manufacturing method are provided.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: April 14, 2009
    Assignee: NEC Corporation
    Inventors: Toshitsugu Sakamoto, Hisao Kawaura, Toshio Baba, Fumiyuki Nihey, Yukinori Ochiai, Hiroo Hongo
  • Publication number: 20070194357
    Abstract: A Schottky photodiode includes a semiconductor layer and a conductive film provided in contact with the semiconductor layer. The conductive film has an aperture and a periodic structure provided around said aperture for producing a resonant state by an excited surface plasmon in a film surface of the conductive film by means of the incident light to the film surface. The photodiode detects near-field light that is generated by at the interface between the conductive film and semiconductor layer the excited surface plasmon. The aperture has a diameter smaller than the wavelength of the incident light.
    Type: Application
    Filed: April 5, 2005
    Publication date: August 23, 2007
    Inventors: Keishi Oohashi, Tsutomu Ishi, Toshio Baba, Junichi Fujikata, Kikuo Makita
  • Publication number: 20070013645
    Abstract: A display method includes: changing a luminance of a display device in accordance with a brightness of surroundings or an operation of a user; and changing a display form of at least one symbol to be displayed depending on the luminance of the display device.
    Type: Application
    Filed: June 29, 2006
    Publication date: January 18, 2007
    Inventor: Toshio Baba
  • Publication number: 20060091557
    Abstract: There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron migration and stress migration, and having a high reliability and a method for manufacturing the same. A semiconductor device having a wiring or a connection plug made of a mixture of a metal and carbon nanotubes berried in a wiring groove or a via hole made in an insulating film on a substrate where a semiconductor chip is fabricated, and its manufacturing method are provided.
    Type: Application
    Filed: December 1, 2003
    Publication date: May 4, 2006
    Applicant: NEC Corporation
    Inventors: Toshitsugu Sakamoto, Hisao Kawaura, Toshio Baba, Fumiyuki Nihey, Yukinori Ochiai, Hiroo Hongo
  • Patent number: 5877510
    Abstract: There are provided on a substrate a block layer having an electron affinity smaller than that of the substrate, a p-type strained superlattice structure having no lattice relaxation and operating as a generation region of spin polarized electrons and a surface layer for accommodating a bending portion of the energy band. The superlattice structure is formed of a multilayer in which a strained well layer and a barrier layer are alternately laminated plural times. The strained well layer has a lattice constant greater than that of the substrate and a thickness equal to or less than a wavelength of electron wave, and the barrier layer has a conduction band lower in energy than that of the strained well layer and a thickness such that an electron in the conduction band can transmit based on tunnel effect. A difference in energy between the band for heavy holes and the band for light holes is further widened in the valence band of the superlattice structure due to compressive stress in the strained well layer.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: March 2, 1999
    Assignee: NEC Corporation
    Inventors: Toshio Baba, Masashi Mizuta, Tsunehiko Omori, Yoshimasa Kurihara, Tsutomu Nakanishi
  • Patent number: 5705827
    Abstract: The tunnel transistor of the present invention has either a junction structure wherein a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor having the reverse conduction type to that of the first semiconductor are connected on a substrate or a laminated layer structure comprising a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor of the reverse conduction type to that of the first semiconductor all laminated on a part of a substrate. The tunnel transistor further includes a fourth semiconductor layer formed on an exposed surface of the second semiconductor, having a forbidden band wider than that of the second semiconductor and containing an ionized impurity therein, a gate electrode formed on the fourth semiconductor layer, and a pair of electrodes individually forming ohmic junctions to the first and third semiconductors.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: January 6, 1998
    Assignee: NEC Corporation
    Inventors: Toshio Baba, Tetsuya Uemura
  • Patent number: 5686739
    Abstract: Disclosed is a three terminal tunnel device exhibiting a tunneling of carriers in a forward direction. The device comprises an intrinsic semiconductor region, an n-type degenerate semiconductor source region abutting one side of the intrinsic semiconductor region, a p-type degenerate semiconductor drain region abutting an opposite side of the intrinsic semiconductor region, an insulation region separating the three semiconductor regions from a semiconductor substrate, and a gate electrode being provided over the intrinsic semiconductor region through an insulation layer, whereby voltage signals to be applied to the gate electrode permit controlling a carrier concentration at a surface of the intrinsic semiconductor region. The device permits controlling a tunneling current of a forward-biased degenerate p-n junction and a current-voltage characteristic manifesting a negative differential resistance with the gate voltage signals.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: November 11, 1997
    Assignee: NEC Corporation
    Inventor: Toshio Baba
  • Patent number: 5589696
    Abstract: A tunnel transistor comprises a semiconductor film (27) between a gate isolating film (17) and parts of first (13) and second (15) semiconductor layers which are formed in a substrate (11) to serve as source and drain regions with a spacer region left therebetween and covered with the semiconductor film. The gate isolating film is over the part of the first semiconductor layer and is made of either an insulating material or a semiconductor material, each of which materials should have a wider forbidden bandwidth than a semiconductor material of the semiconductor film, such as silicon dioxide, silicon nitride, or aluminium nitride, or gallium phosphide for silicon, or AlGaAs fox gallium arsenide. A source electrode is formed on an uncovered area of the first semiconductor layer. The semiconductor film forms a tunnel junction with the first semiconductor layer and an ohmic junction with the second semiconductor layer, which junction may be either a homojunction or a heterojunction.
    Type: Grant
    Filed: October 14, 1992
    Date of Patent: December 31, 1996
    Assignee: NEC Corporation
    Inventor: Toshio Baba
  • Patent number: 4903091
    Abstract: A heterojunction transistor has a first semiconductor layer of a semi-insulating or a low impurity concentration, a second semiconductor layer formed on the first semiconductor layer and made of such a semiconductor material that, in cooperation with the first semiconductor layer, a first energy recess for electrons and a second energy recess for holes are respectively formed at the bottom of the conduction band and at the top of the valence band to constitute a conductive channel, a third semiconductor layer formed on the second semiconductor layer and forming a PN-junction with the upper surface of the second semiconductor layer to inject carriers into the conductive channel, a control electrode for applying an input signal to the third semiconductor layer, and a ground and an output electrode formed on the second semiconductor layer on the opposite sides of the third semiconductor layer.
    Type: Grant
    Filed: May 23, 1988
    Date of Patent: February 20, 1990
    Assignee: NEC Corporation
    Inventors: Toshio Baba, Masaki Ogawa, Keiichi Ohata
  • Patent number: 4839120
    Abstract: A method of extruding a ceramic batch supplied from a vacuum auger machine into a formed body by a plunger molding machine, included the steps of loosening and crushing a supplied ceramic batch in the vacuum auger machine, extruding the loosened and crushed ceramic batch from the vacuum auger machine into a formed columnar body which is of a size able to be inserted into a cylinder of the plunger molding machine, and extruding the formed columnar body from the plunger molding machine to form a formed body of a predetermined shape. An apparatus for extruding a ceramic batch includes a vacuum auger machine having of a vacuum kneading section for kneading a ceramic material to produce a ceramic batch, a columnar body forming section for forming the kneaded ceramic material into a columnar body, and a batch transfer section having an auger for transferring the ceramic batch to the columnar body forming section.
    Type: Grant
    Filed: February 18, 1988
    Date of Patent: June 13, 1989
    Assignee: NGK Insulators, Ltd.
    Inventors: Toshio Baba, Hajime Matsushita, Yasuji Katsuragawa
  • Patent number: 4792832
    Abstract: The superlattice type semiconductor material has a multilayered structure of first layers of semiconductor containing impurities and having a thickness thinner than electron or hole wavelength and second layers of semiconductor free from impurities or insulator having such a thickness that electrons or holes may penetrate by tunneling effect, the first and second layers being alternately piled. Electrons or holes distribute uniformly over the entire of the multilayered structure to show a property of uniform semiconductor material.
    Type: Grant
    Filed: April 24, 1987
    Date of Patent: December 20, 1988
    Assignee: NEC Corporation
    Inventors: Toshio Baba, Takashi Mizutani, Masaki Ogawa
  • Patent number: 4695857
    Abstract: The superlattice type semiconductor material has a multilayered structure of first layers of semiconductor containing impurities and having a thickness thinner than electron or hole wavelength and second layers of semiconductor free from impurities or insulator having such a thickness that electrons or holes may penetrate by tunneling effect, the first and second layers being alternately piled. Electrons or holes distribute uniformly over the entire of the multilayered structure to show a property of uniform semiconductor material.
    Type: Grant
    Filed: June 25, 1984
    Date of Patent: September 22, 1987
    Assignee: NEC Corporation
    Inventors: Toshio Baba, Takashi Mizutani, Masaki Ogawa
  • Patent number: 4601957
    Abstract: A method for producing a thin tin and nickel plated steel sheet having a surface structure in which the distribution of numerous nodules of metallic tin are observed by using an electron microscope on an iron-tin-nickel alloy layer formed on a steel sheet which comprises electroplating nickel on the steel sheet which is anodically treated in an alkaline electrolyte with a pH of above 10 followed by electrotinplating the nickel plated steel sheet, reflowing, quenching, and then chromate treating the tin and nickel plated steel sheet.This tin and nickel plated steel sheet is suitable for welded can materials since it is excellent in corrosion resistance after lacquering and weldability.
    Type: Grant
    Filed: August 29, 1985
    Date of Patent: July 22, 1986
    Assignee: Toyo Kohan Co., Ltd.
    Inventors: Terunori Fujimoto, Yasuhiko Nakagawa, Toshio Baba, Hirokazu Moriyama, Akio Miyachi, Tsuneo Inui