Patents by Inventor Toshio Fujioka

Toshio Fujioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11162254
    Abstract: Provided is a column-beam joint structure 1, wherein a plurality of thick-walled portions 3, notches 7, and narrow-width portions 9a on a central side of a flange plate 5 are formed integrally, cutting (dividing) is effected at a cut line 8, and the thick-walled portion 3 is welded and joined to a column 2a.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: November 2, 2021
    Assignee: SDR TECHNOLOGY CO., LTD.
    Inventor: Toshio Fujioka
  • Publication number: 20190368187
    Abstract: Provided is a column-beam joint structure 1, wherein a plurality of thick-walled portions 3, notches 7, and narrow-width portions 9a on a central side of a flange plate 5 are formed integrally, cutting (dividing) is effected at a cut line 8, and the thick-walled portion 3 is welded and joined to a column 2a.
    Type: Application
    Filed: February 17, 2017
    Publication date: December 5, 2019
    Inventor: Toshio FUJIOKA
  • Patent number: 6332112
    Abstract: An inspecting apparatus includes a measuring device and a processing unit. The measuring device is provided with a vibration detector for detecting the vibration of a steam trap when a valve thereof is closed. The processing unit is provided with a performance deterioration value calculator for converting the detected vibration level of the steam trap into a sealing performance deterioration value representing a deterioration level of the sealing performance of the valve of the steam trap under a reference steam pressure value using a working steam pressure value, a display for displaying a rank of the sealing performance obtained based on the sealing performance deterioration value, and a trap list storage for storing the sealing performance deterioration value and the rank of the sealing performance as well as ID information of the steam trap. The steam trap can be more precisely inspected.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: December 18, 2001
    Assignee: Miyawaki Inc.
    Inventors: Hiroshi Shukunami, Toshio Fujioka
  • Patent number: 5300446
    Abstract: On an insulating film (12) covering the surface of a semiconductor substrate (10), a gate electrode layer (14), a gate insulating film (16), and a semiconductor layer (18) such as silicon are sequentially deposited to form an under-gated MOS transistor. A flat coating film such as resist is formed covering the semiconductor layer (18). The coating film is then etched back to expose the surface of the semiconductor layer (18) at the area above the gate electrode layer (14). The left coating film is used as the mask for the selective growth of a mask material layer (24) such as tungsten on the exposed surface of the semiconductor layer (18) with a side-projection. After removing the left coating film, impurity ions such as BF2 are selectively injected in the semiconductor layer (18) using the mask material layer (24) as the mask to form a source region (18S) and a drain region (18D).
    Type: Grant
    Filed: May 5, 1993
    Date of Patent: April 5, 1994
    Assignee: Yamaha Corporation
    Inventor: Toshio Fujioka
  • Patent number: 4866003
    Abstract: For enhancement of device stability, there is disclosed a semiconductor device fabricated on a semiconductor substrate comprising (a) source and drain regions formed in a surface portion of the semiconductor substrate and spaced from each other by a channel region, (b) a gate insulating film formed on the channel region, (c) a gate electrode structure formed on the gate insulating film, and (d) a passivation film of an insulating material covering the gate electrode structure and containing hydrogen-bonded-silicons equal in number to or less than 5.times.10.sup.21 per cm.sup.3, and the unstable hydrogen-bonded-silicons are decreased in number so that the semiconductor device only have a decreased trap density which results in stable operation.
    Type: Grant
    Filed: November 20, 1987
    Date of Patent: September 12, 1989
    Assignee: Yamaha Corporation
    Inventors: Katsuyuki Yokoi, Shigeru Suga, Toshio Fujioka