Patents by Inventor Toshio Haba

Toshio Haba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8387255
    Abstract: The fine pattern mold that includes a roll, a buffer tube with inner peripheral surface is in contact with an outer peripheral surface of the roll, and a stamper tube in which its inner peripheral surface is in contact with an outer peripheral surface of the buffer tube and a fine concave/convex pattern is formed on its outer peripheral surface, wherein the buffer tube has a larger coefficient of linear expansion and a smaller elastic modulus than those of the stamper tube.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: March 5, 2013
    Assignee: Hitachi Industrial Equipment Systems Co., Ltd.
    Inventors: Masahiko Ogino, Mitsuru Hasegawa, Kenya Ohashi, Akihiro Miyauchi, Hitoshi Suzuki, Toshio Haba, Haruo Akahoshi
  • Publication number: 20120067507
    Abstract: The fine pattern mold that includes a roll, a buffer tube with inner peripheral surface is in contact with an outer peripheral surface of the roll, and a stamper tube in which its inner peripheral surface is in contact with an outer peripheral surface of the buffer tube and a fine concave/convex pattern is formed on its outer peripheral surface, wherein the buffer tube has a larger coefficient of linear expansion and a smaller elastic modulus than those of the stamper tube.
    Type: Application
    Filed: November 30, 2011
    Publication date: March 22, 2012
    Inventors: Masahiko OGINO, Mitsuru Hasegawa, Kenya Ohashi, Akihiro Miyauchi, Hitoshi Suzuki, Toshio Haba, Haruo Akahoshi
  • Patent number: 8083515
    Abstract: The fine pattern mold comprises: that includes a roll, a buffer tube with inner peripheral surface is in contact with an outer peripheral surface of the roll, and a stamper tube in which its inner peripheral surface is in contact with an outer peripheral surface of the buffer tube and a fine concave/convex pattern is formed on its outer peripheral surface, wherein the buffer tube has a larger coefficient of linear expansion and a smaller elastic modulus than those of the stamper tube.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: December 27, 2011
    Assignee: Hitachi Industrial Equipment Systems, Co., Ltd.
    Inventors: Masahiko Ogino, Mitsuru Hasegawa, Kenya Ohashi, Akihiro Miyauchi, Hitoshi Suzuki, Toshio Haba, Haruo Akahoshi
  • Publication number: 20110143196
    Abstract: Objects of the present invention are to improve the adhesion and processing characteristics of electrode composite layers and to provide a lithium secondary battery by which a decrease in battery capacity during high-temperature storage at 50° C. or higher is suppressed. The lithium secondary battery of the present invention comprises a positive electrode capable of storing and releasing lithium ions, a negative electrode capable of storing and releasing lithium ions, a separator disposed between the positive electrode and the negative electrode, and an electrolyte, wherein the negative electrode or the electrolyte contains a nonvolatile liquid.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 16, 2011
    Inventors: Takefumi OKUMURA, Ryo Inoue, Toshio Haba, Chieko Araki
  • Publication number: 20110114368
    Abstract: A small-sized electronic circuit component comprising micro-wiring and a method for manufacturing the same are provided. The electronic circuit component is manufactured by a manufacturing method comprising the steps of forming a recessed portion which is to be a three-dimensional wiring in the surface of an insulating base material of the electronic circuit component comprising the wiring, forming a first metal layer which is to be an electroplated conductive layer on the surface of the insulating base material including the recessed portion, selectively forming a second metal layer which is to be the wiring only in the recessed portion which is to be the wiring, and removing the first metal layer formed on the surface other than in the recessed portion which is to be the wiring.
    Type: Application
    Filed: June 25, 2009
    Publication date: May 19, 2011
    Inventors: Hiroshi Nakano, Hitoshi Suzuki, Toshio Haba, Haruo Akahoshi
  • Patent number: 7922887
    Abstract: The present invention provides a method for producing a metal structure comprising a substrate and a metal film formed on the substrate; comprising the steps of providing surface having irregularities made of a electrical conductor in the area of the substrate where the metal body or film is to be formed; and preferentially forming the metal body or film by electroplating in the area provided with the conductive surface having irregularities. The plating bath may preferably contain an additive compound such as a cyanine dye which is capable of suppressing the plating reaction, and which loses such plating-suppressing effect with the progress of the plating reaction. The metal film can be produced by electroplating in the area provided with the surface having irregularities.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: April 12, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Haba, Hiroshi Yoshida, Haruo Akahoshi, Hitoshi Suzuki
  • Publication number: 20100181100
    Abstract: A copper wiring board having fine wiring, and a method for manufacturing the same are provided. The copper wiring board of the present invention is a wiring board comprising an insulating substrate, a plurality of wire trenches formed in the insulating substrate, and wires filled in the wire trenches, wherein when any two of the wires are selected, and cross sections are taken perpendicular to a direction of current flow in the wires, a wire width in one wire cross section is narrower than a wire width in the other wire cross section, and a wire thickness in the one wire cross section is thicker than a wire thickness in the other wire cross section.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 22, 2010
    Inventors: Hiroshi NAKANO, Hitoshi SUZUKI, Toshio HABA, Haruo AKAHOSHI, Hiroshi YOSHIDA, Akira CHINDA
  • Publication number: 20090057156
    Abstract: It is an object of the present invention to alleviate a work for removing an unnecessary metal layer when wiring and vias are formed on a substrate by electroplating. An additive is added to a plating solution to be used for electroplating. The additive has a plating reaction suppressing capability, but has a characteristic that the plating reaction suppressing capability is reduced as the plating reaction progresses. The additive has a capability for increasing a metal deposition overpotential and has a characteristic that the metal deposition overpotential is reduced as the reaction progresses. As a result, the metal can be deposited selectively in a trench and a via formed on the substrate. When a wiring and a via are formed on the substrate, the trench and the via having a predetermined surface roughness are formed on the substrate.
    Type: Application
    Filed: August 13, 2008
    Publication date: March 5, 2009
    Inventors: Toshio Haba, Haruo Akahoshi, Hitoshi Suzuki, Akira Chinda
  • Publication number: 20080299247
    Abstract: There is provided a fine pattern mold capable of transferring a fine concave/convex pattern accurately without causing deformation of the fine concave/convex pattern itself. The fine patter mold comprises: a roll; a buffer tube whose inner peripheral surface is in contact with an outer peripheral surface of the roll; and a stamper tube in which its inner peripheral surface is in contact with an outer peripheral surface of the buffer tube and a fine concave/convex pattern is formed on its outer peripheral surface, wherein the buffer tube has a larger coefficient of linear expansion and a smaller elastic modulus than those of the stamper tube.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 4, 2008
    Inventors: Masahiko Ogino, Mitsuru Hasegawa, Kenya Ohashi, Akihiro Miyauchi, Hitoshi Suzuki, Toshio Haba, Haruo Akahoshi
  • Publication number: 20080251387
    Abstract: It is an object of the present invention to provide a wiring board having high-density wiring with a controlled shape without masking by a resist film and a production method thereof. In the present invention, the production method of a wiring board having copper wiring on an insulating substrate includes the steps of forming a metal seed layer on the insulating substrate, the metal seed layer having a roughened shape in a portion on which the copper wiring or a bump is to be formed, and forming an electroplated film of copper or an alloy of copper through electroplating on the portion of the metal seed layer having the roughened shape. A substance for suppressing the plating reaction is added to a plating bath to provide an angle of 90 degrees or smaller between a surface of the insulating substrate and a side of the electroplated film.
    Type: Application
    Filed: June 12, 2008
    Publication date: October 16, 2008
    Inventors: Toshio Haba, Hiroshi Yoshida, Haruo Akahoshi, Hitoshi Suzuki, Akira Chinda
  • Publication number: 20070287289
    Abstract: [Problem to be Solved] An object of the present invention is to provide a method of forming a conductive pattern having an excellent uniformity of film thickness within the surface of a substrate independently of the density of the pattern. [Solution] The production method of a conductive pattern in accordance with the present invention comprises the step of electroplating for forming a conductive pattern by electroplating on a metal seed layer formed on an insulated substrate using a plating bath containing an accelerator for reducing the deposition overpotential of a plated metal.
    Type: Application
    Filed: June 11, 2007
    Publication date: December 13, 2007
    Inventors: Toshio Haba, Hitoshi Suzuki, Naohito Satou, Haruo Akahoshi, Hiroshi Yoshida, Akira Chinda
  • Publication number: 20060180472
    Abstract: The present invention provides a method for producing a metal structure comprising a substrate and a metal film formed on the substrate; comprising the steps of providing surface having irregularities made of a electrical conductor in the area of the substrate where the metal body or film is to be formed; and preferentially forming the metal body or film by electroplating in the area provided with the conductive surface having irregularities. The plating bath may preferably contain an additive compound such as a cyanine dye which is capable of suppressing the plating reaction, and which loses such plating-suppressing effect with the progress of the plating reaction. The metal film can be produced by electroplating in the area provided with the surface having irregularities.
    Type: Application
    Filed: January 27, 2006
    Publication date: August 17, 2006
    Inventors: Toshio Haba, Hiroshi Yoshida, Haruo Akahoshi, Hitoshi Suzuki
  • Publication number: 20060163725
    Abstract: It is an object of the present invention to provide a wiring board having high-density wiring with a controlled shape without masking by a resist film and a production method thereof. In the present invention, the production method of a wiring board having copper wiring on an insulating substrate includes the steps of forming a metal seed layer on the insulating substrate, the metal seed layer having a roughened shape in a portion on which the copper wiring or a bump is to be formed, and forming an electroplated film of copper or an alloy of copper through electroplating on the portion of the metal seed layer having the roughened shape. A substance for suppressing the plating reaction is added to a plating bath to provide an angle of 90 degrees or smaller between a surface of the insulating substrate and a side of the electroplated film.
    Type: Application
    Filed: August 17, 2005
    Publication date: July 27, 2006
    Inventors: Toshio Haba, Hiroshi Yoshida, Haruo Akahoshi, Hitoshi Suzuki, Akira Chinda
  • Publication number: 20050087447
    Abstract: An object of the present invention is to improve the reliability and the yield of production of semiconductor integrated circuit devices by filling copper in the inside of features having a high aspect ratio for forming multi-layer interconnections composed of a plurality of interconnection layers which are connected to one another and to a copper electroplating bath suitable therefor. In the present invention, when the features are filled with copper, the use of a copper electroplating bath with an addition of cyanine dyes, for example, indolium compounds allows the copper plating to proceed preferentially from the bottoms of the features.
    Type: Application
    Filed: November 26, 2004
    Publication date: April 28, 2005
    Inventors: Toshio Haba, Takeyuki Itabashi, Haruo Akahoshi, Shinichi Fukada
  • Publication number: 20030085467
    Abstract: A plating method comprising using a plating solution containing an additive satisfying the following conditions:
    Type: Application
    Filed: December 3, 2002
    Publication date: May 8, 2003
    Inventors: Kinya Kobayashi, Akihiro Sano, Takeyuki Itabashi, Toshio Haba, Haruo Akahoshi, Shinichi Fukada
  • Patent number: 6511588
    Abstract: A plating method comprising using a plating solution containing an additive satisfying the following conditions: 0.005×h2/w<D/&kgr;<0.5×h2/w, and 0.01≦&THgr;≦0.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: January 28, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kinya Kobayashi, Akihiro Sano, Takeyuki Itabashi, Toshio Haba, Haruo Akahoshi, Shinichi Fukada
  • Publication number: 20020084191
    Abstract: An object of the present invention is to improve the reliability and the yield of production of semiconductor integrated circuit devices by filling copper in the inside of features having a high aspect ratio for forming multi-layer interconnections composed of a plurality of interconnection layers which are connected to one another and to a copper electroplating bath suitable therefor. In the present invention, when the features are filled with copper, the use of a copper electroplating bath with an addition of cyanine dyes, for example, indolium compounds allows the copper plating to proceed preferentially from the bottoms of the features.
    Type: Application
    Filed: June 26, 2001
    Publication date: July 4, 2002
    Inventors: Toshio Haba, Takeyuki Itabashi, Haruo Akahoshi, Shinichi Fukada
  • Publication number: 20020030283
    Abstract: The semiconductor device is provided with an insulator layer having a via-stud on a semiconductor substrate, the via-stud being formed in a via-hole through a barrier layer formed of an inorganic compound layer or a high melting point metal layer formed on an inner surface of the via-hole, the via-stud being made of the same metal as a metal composing the barrier layer. The semiconductor device can be obtained by forming the barrier layer on the inner surface of the via-hole in the semiconductor substrate, then treating the substrate with a treatment solution containing a complex forming agent, immersing the treated substrate into an electroless plating solution, bringing a member made of the same metal as a metal formed by the electroless plating in contact with the electroless plating solution, and electrically connecting the member to the barrier layer to perform electroless plating.
    Type: Application
    Filed: September 25, 2001
    Publication date: March 14, 2002
    Inventors: Takeyuki Itabashi, Toshio Haba, Haruo Akahoshi
  • Patent number: 6300244
    Abstract: When a wiring conductor is formed on a semiconductor substrate, a via-hole or a trench is formed by directly performing electroless plating on a barrier layer containing a very small depressed portion such as the via-hole or the trench in an insulator layer without using a dry metallized method or a substitutive plating method. The semiconductor device is provided with an insulator layer having a via-stud on a semiconductor substrate, the via-stud being formed in a via-hole through a barrier layer formed of an inorganic compound layer or a high melting point metal layer formed on an inner surface of the via-hole, the via-stud being made of the same metal as a metal composing the barrier layer.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: October 9, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Takeyuki Itabashi, Toshio Haba, Haruo Akahoshi