Abstract: An image processing apparatus capable of performing flexible, high speed processing, wherein a memory region emptied due to a change of display resolution can be used as a texture memory, increase of an overhead such as switching pages can be prevented, and a decline in the performance is not caused. A built-in DRAM inside a semiconductor chip has a configuration for storing display data and the texture data required by at least one graphic element. The texture data can be stored in portions other than the display regions, so the built-in DRAM can be used efficiently and an image processing apparatus achieving both high speed operation and a reduction of power consumption can be realized.

Abstract: An image processing apparatus capable of performing flexible, high speed processing, wherein a memory region emptied due to a change of display resolution can be used as a texture memory, increase of an overhead such as switching pages can be prevented, and a decline in the performance is not caused. A built-in DRAM inside a semiconductor chip has a configuration for storing display data and the texture data required by at least one graphic element. The texture data can be stored in portions other than the display regions, so the built-in DRAM can be used efficiently and an image processing apparatus achieving both high speed operation and a reduction of power consumption can be realized.

Abstract: A signal processing apparatus for linear interpolation capable of performing operations to obtain suitable original data even when an interpolation coefficient &agr; is 1.0, wherein a correction term selects A when &agr;=0×FF (&agr;=1.0) and selects B when the bit is 0. The selected data becomes an element of addition by being shifted for the number of bits of &agr;. A product summation operation term uses the upper 8 bits of the result of multiplication of 8 bits×8 bits and shifts the 8-bit result of operation 8 bits to the left so as to enable further addition of the product summation operation term. An adder adds the shifted correction term, the partial products out—0 to out—7, and the product summation operation term and outputs the upper 8 bits as the result of the operation.

Abstract: An image processing apparatus capable of performing flexible, high speed processing, wherein a memory region emptied due to a change of display resolution can be used as a texture memory, increase of an overhead such as switching pages can be prevented, and a decline in the performance is not caused. A built-in DRAM inside a semiconductor chip has a configuration for storing display data and the texture data required by at least one graphic element. The texture data can be stored in portions other than the display regions, so the built-in DRAM can be used efficiently and an image processing apparatus achieving both high speed operation and a reduction of power consumption can be realized.

Abstract: N expansion bits are added to the LSB side of original data of m bits and thereby expanded data of (m+n) bits is obtained. In the case of m.ltoreq.n, each bit of original data of m bits is repeatedly assigned to the LSB side of original data. In the case of m>n, n bits on the MSB side of the original data of m bits are added to the LSB side of original data. Since the bit values of expansion bits vary corresponding to the values of the original data, a bit expansion can be smoothly performed in the full range.