Abstract: A semiconductor integrated circuit comprises a first and second common wiring layers common to a plurality of types of products and independent of a user circuit, a customized layer provided between the first common wiring layer and the second common wiring layer and which is configured to form the user circuit. The second common wiring layer is formed above an upper layer of the first common wiring layer, and an universal logic cell is wired to the first and second common wiring layers and the customized layer. A power supply wiring, which is connected to a power supply pad, which is connected to an external power supply, is formed through the second common wiring layer, and the power supply wiring is formed in the same layer as the power supply pad and extends to an internal circuit area in which the universal logic cell is formed.

Abstract: There is provided a semiconductor device that operates at an internal clock based on a system clock and inputs/outputs data in synchronization with the internal clock. The semiconductor device includes a phase locked loop generating the internal clock and a switching element switching delay paths to be inserted into a feedback loop to the phase locked loop in accordance with data input/output in the semiconductor device.

Abstract: A three-state buffer operating at a 3V power source supplies a three-state signal to a bus line pulled up to a 5V power source line. The three-state buffer includes CMOS transistors each receiving an output signal from a pre-stage buffer arid a transfer gate connected between the output of the CMOS transistors and the output terminal of the integrated circuit. The back-gate of the p-channel transistor of the CMOS is maintained at an intermediate potential between the 3V source line and the ground line while being in a floating state. The intermediate potential is presented by a serial three transistors. A low power dissipation and a high speed operation can be obtained by the circuit.

Abstract: Disclosed is a semiconductor integrated circuit device with an electrode pad having a lower conductive film (second aluminum film) formed on a semiconductor substrate, an upper conductive film (third aluminum film) formed through an interlayer insulating film (second interlayer insulating film) on the lower conductive film. The upper conductive film is electrically connected to the lower conductive film by a minute through hole, and extends to a planar region where the lower conductive film is not present. That extending portion of the upper conductive film serves as a wire bonding portion. This design allows the through hole to be formed as small as the inner through hole of the integrated circuit, so that this electrode pad will have an improved bonding characteristic while being able to cope with a through-hole filling step.