Abstract: A method for treating or preventing a thrombosis in a person in need thereof comprising disposing in or on an article an effective antithrombotic amount of a composition and providing the article to be in close proximity to the skin of the person, the composition comprising (i) alumina, (ii) at least one substance selected from the group consisting of silica and titanium oxide and (iii) at least one element or compound selected from the group consisting of platinum, a platinum compound, palladium, a palladium compound, iridium, an iridium compound, rhodium and a rhodium compound.

Abstract: Disclosed herewith is a semiconductor device having an SRAM cell array capable of easily evaluating the performance of transistors and the systematic fluctuation of wiring capacity/resistance. In order to form an inversion circuit required to form a ring oscillator, a test cell is disposed at each of the four corners of the SRAM cell array and the ring oscillator is operated while charging/discharging the subject bit line. Concretely, the ring oscillator is formed on a memory cell array and the ring oscillator includes test cells disposed at least at the four corners of the memory cell array respectively. At this time, a wiring that is equivalent to a bit line is used to connect the test cells to each another.

Abstract: Disclosed herewith is a semiconductor device having an SRAM cell array capable of easily evaluating the performance of transistors and the systematic fluctuation of wiring capacity/resistance. In order to form an inversion circuit required to form a ring oscillator, a test cell is disposed at each of the four corners of the SRAM cell array and the ring oscillator is operated while charging/discharging the subject bit line. Concretely, the ring oscillator is formed on a memory cell array and the ring oscillator includes test cells disposed at least at the four corners of the memory cell array respectively. At this time, a wiring that is equivalent to a bit line is used to connect the test cells to each another.

Abstract: An SRAM cell 1 includes inverters 10, 20, N-type FETs 32, 34, 36, 38, word lines 42, 44, bit lines 46, 48, and voltage applying circuits 50, 60. The voltage applying circuits 50, 60 apply a voltage Vdd to the word lines 42, 44 at the time of a read operation of the SRAM cell 1. The voltage applying circuits 50, 60 apply a voltage (Vdd+?) to the word lines 42, 44 at the time of a write operation of the SRAM cell 1. Here, ?>0. Namely, the SRAM cell 1 is configured in such a manner that a voltage applied to word lines 42, 44 at the time of the write operation is higher than at the time of the read operation.

Abstract: The SRAM cell 1 includes inverters 10, 20, N-type FETs (Field Effect Transistors) 32, 34, 36, 38, word lines 42, 44, and bit lines 46, 48. A gate width W2 and gate length L2 of the FETs 32, 34, 36, 38 are equal to a gate width W3 and gate length L3 of the FETs 12, 22, respectively. In particular, in this embodiment, a gate width W4 and gate length L4 of the FETs 14, 24 are also equal to W2 (=W3) and L2 (=L3), respectively. Namely, the SRAM cell 1 is designed in such a manner that W2=W3=W4, and L2=L3=L4.

Abstract: A method for treating or preventing a thrombosis in a person in need thereof comprising disposing in or on an article an effective antithrombotic amount of a composition and providing the article to be in close proximity to the skin of the person, the composition comprising (i) alumina, (ii) at least one substance selected from the group consisting of silica and titanium oxide and (iii) at least one element or compound selected from the group consisting of platinum, a platinum compound, palladium, a palladium compound, iridium, an iridium compound, rhodium and a rhodium compound.

Abstract: The SRAM cell 1 includes inverters 10, 20, N-type FETs (Field Effect Transistors) 32, 34, 36, 38, word lines 42, 44, and bit lines 46, 48. A gate width W2 and gate length L2 of the FETs 32, 34, 36, 38 are equal to a gate width W3 and gate length L3 of the FETs 12, 22, respectively. In particular, in this embodiment, a gate width W4 and gate length L4 of the FETs 14, 24 are also equal to W2 (=W3) and L2 (=L3), respectively. Namely, the SRAM cell 1 is designed in such a manner that W2=W3=W4, and L2=L3=L4.

Abstract: An SRAM cell 1 includes inverters 10, 20, N-type FETs 32, 34, 36, 38, word lines 42, 44, bit lines 46, 48, and voltage applying circuits 50, 60. The voltage applying circuits 50, 60 apply a voltage Vdd to the word lines 42, 44 at the time of a read operation of the SRAM cell 1. The voltage applying circuits 50, 60 apply a voltage (Vdd+?) to the word lines 42, 44 at the time of a write operation of the SRAM cell 1. Here, ?>0. Namely, the SRAM cell 1 is configured in such a manner that a voltage applied to word lines 42, 44 at the time of the write operation is higher than at the time of the read operation.

Abstract: The present invention is related to a composition, which comprises alumina, at least one of silica and titanium oxide, at least one of platinum, palladium, iridium, rhodium, and compounds thereof, and at least one of silver and a silver compound in order to provide a powder and/or a composition and a fiber having incorporated thereinto a powder and/or a composition, being capable of uniformly emit far infrared rays at high efficiency as well as having excellent durability and transparency. In addition, the present invention is related to a mixture containing the above composition and a synthetic polymer material, a fiber having incorporated thereinto the above mixture, and fiber products using the above fiber.

Abstract: An antithrombotic composition comprising (i) alumina, (ii) at least one substance selected from silica and titanium oxide, and (iii) at least one element or compound selected from platinum or a platinum compound, palladium or a palladium compound, iridium or an iridium compound and rhodium or a rhodium compound, and an article such as clothing, bedding and so forth comprising the composition. The antithrombotic property can be worked by the composition or the article without lapsing into bleeding tendency.

Abstract: A semiconductor memory in which a layout margin at the contact hole between wiring layers of a SRAM does not need and the wiring capacity at bit lines is reduced and the high speed processing is made to be possible is provided. The SRAM is constituted of a pair of driving transistors Qd1 and Qd2, a pair of transferring transistors Qt1 and Qt2, high resistance loads R1 and R2, a pair of bit lines BL1 and BL2, and a VCC line and a GND line. Gate electrodes of each transistor and word lines are formed at a first layer, the high resistance loads are formed at a second layer, the VCC line and the GND line are formed at a third layer, and the bit lines are formed at a fourth layer. A shared contact hole using for connecting the high resistance loads to the source/drain area of transistors does not penetrate the other conductive layers. Therefore, the layout margin between the shared contact hole and the other conductive layers becomes unnecessary and the reduction of the cell size becomes possible.

Abstract: A gate electrode is formed on a first conductive type semiconductor. Next, a second conductive type first impurity is selectively introduced in a drain formation planned region at a surface of the semiconductor substrate to form a first diffusion layer. Then, a second conductive type second impurity having a diffusion coefficient smaller than that of the first impurity is selectively introduced in a source formation planned region at the surface of the semiconductor substrate to form a second diffusion layer. Thereafter, a side wall is formed on a side surface of the gate electrode. Then, a second conductive type third impurity is introduced at the surface of the semiconductor substrate at a density higher than the first and second impurities, using the gate electrode and the side wall as a mask.

Abstract: A multi-input semiconductor logic device capable of high-speed operation includes a first to fifth source/drain regions formed in an active area, and first to fourth gate electrodes formed over the active area through a gate insulating layer. The first to fifth source/drain regions are arranged along an axis of the active area. The second and fourth source/drain regions are located to be adjacent to the first source/drain region at each side of the first source/drain region. The third and fifth source/drain regions are located to be adjacent to the second and fourth source/drain regions, respectively. The first gate electrode is located between the first and second source/drain regions. The second gate electrode is located between the first and fourth source/drain regions. The third gate electrode is located between the second and third source/drain regions. The fourth gate electrode is located between the fourth and fifth source/drain regions.

Abstract: A recording and/or playback apparatus that uses a tape cassette having protrusions is equipped with a mounting section, a lid, a holder, and a detection mechanism. The mounting section is to be mounted with a tape cassette. The lid, which is to open or close the mounting section, is provided so as to be movable between a closed position for closing the mounting section and an open position for opening the mounting section. The lid is provided in front of the holder. The holder holds a tape cassette that has been inserted in the apparatus, and causes the tape cassette held by the holder to be mounted in the mounting section when the lid is moved to the closed position. The detection mechanism indicates whether a tape cassette is mounted in the mounting section. When the lid is located at the closed position, the protrusion of the tape cassette that is mounted in the mounting section manipulates the detection mechanism so that the detection mechanism projects from the front surface of the lid.

Abstract: In a method for manufacturing a BiMOS device, first and second semiconductor layers are formed on a semiconductor substrate, first and second field insulating layers are formed by using a LOCOS process on said first and second semiconductor layers, respectively. The first field insulating layer partitions a bipolar transistor area and a MOS transistor area, and the second field insulating layer is formed on a base-emitter junction region of the first semiconductor layer. Then, impurities are introduced via the second field insulating layer into the first semiconductor layer to form a base region therein. Then, an emitter opening is perforated in the second field insulating layer, and a polycrystalline silicon layer is formed on the second field insulating layer. Then, impurities of a first conductivity type are introduced into the polycrystalline silicon layer, and a heating operation is performed upon the polycrystalline silicon layer to form an emitter region.

Abstract: A semiconductor static random access memory device has a memory cell array assigned a central area of a major surface of a silicon substrate and a peripheral circuit assigned a peripheral area of the major surface, and the memory cell array and the peripheral circuit are covered with a multiple-layered inter-level insulating structure; and the memory cells are associated with various conductive lines extending on different inter-level insulating layers, and dummy strips are inserted on the different inter-level insulating layers so as to make the multiple-layered inter-level insulating structure constant in thickness, thereby preventing a gate electrode of a component bulk transistor of the peripheral circuit from over-etching during formation of contact holes.

Abstract: In a method for manufacturing a BiMOS device, first and second semiconductor layers are formed on a semiconductor substrate, first and second field insulating layers are formed by using a LOCOS process on said first and second semiconductor layers, respectively. The first field insulating layer partitions a bipolar transistor area and a MOS transistor area, and the second field insulating layer is formed on a base-emitter junction region of the first semiconductor layer. Then, impurities are introduced via the second field insulating layer into the first semiconductor layer to form a base region therein. Then, an emitter opening is perforated in the second field insulating layer, and a polycrystalline silicon layer is formed on the second field insulating layer. Then, impurities of a first conductivity type are introduced into the polycrystalline silicon layer, and a heating operation is performed upon the polycrystalline silicon layer to form an emitter region.

Abstract: A semiconductor device with an LDD structure type MOS transistor is fabricated by forming a gate electrode on a semiconductor layer of a first conductivity type and a source/drain region in the semiconductor layer, the source/drain region having a high impurity concentration region and a low impurity concentration region of a second conductivity type. A pocket of the first conductivity type is formed in contact with the low impurity concentration region only on a drain region side and immediately under the low concentration region of the second conductivity type. The pocket formed only on the drain side can suppress the short channel effect and also the hot carrier generation without lowering the current capacity on the source side where no pocket is present.

Abstract: A "BiCMOS" semiconductor integrated circuit, a gate oxide film 110 and a polysilicon film are grown on a semiconductor substrate, and after phosphorus is doped, the polysilicon film is patterned to form gate electrodes 112a and 112b and an emitter electrode 112c. A heat treatment is performed to form an emitter diffused region 113. Phosphorus and boron are selectively implanted with a low impurity concentration, respectively, to form a LDD N.sup.- region 114 and a LDD P.sup.- region 115. Thereafter, a side wall 116 is formed, and boron is implanted into areas B and C so as to form P.sup.+ source/drain regions 117 and a graft base region 18, respectively. Phosphorus is implanted to form N.sup.+ source/drain regions 119.

Abstract: In a method for manufacturing a "BiCMOS" semiconductor integrated circuit, a gate oxide film 110 and a polysilicon film are grown on a semiconductor substrate, and after phosphorus is doped, the polysilicon film is patterned to form gate electrodes 112a and 112b and an emitter electrode 112c. A heat treatment is performed to form an emitter diffused region 113. Phosphorus and boron are selectively implanted with a low impurity concentration, respectively, to form a LDD N.sup.- region 114 and a LDD P.sup.- region 115. Thereafter, a side wall 116 is formed, and boron is implanted into areas B and C so as to form P.sup.+ source/drain regions 117 and a graft base region 18, respectively. Phosphorus is implanted to form N.sup.+ source/drain regions 119.