Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.

Abstract: A welding start position detecting apparatus for a welding robot in which a first reference voltage and a second reference voltage having different voltage levels are set as comparison reference voltages in which, during a preset time period after start of searching operation, a voltage for detection of the welding start position is compared with the first reference voltage having a higher sensitivity and, when the welding start position detecting voltage comes across a level of the first reference voltage, the first reference voltage is switched to the second reference voltage having a lower sensitivity for comparing operation of the welding start position detecting voltage with the second reference voltage to thereby enable the detection of the welding start position on a base material even when an impedance around a welding torch changes.

Abstract: A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.

Abstract: A roller conveyor in which articles are supported by idler rollers carried by a main frame and conveyed as the idler rollers are driven into rotation. A plurality of first idler rollers are arranged in one of two side frames of the main frame. A plurality of second idler rollers capable of supporting articles in pair with the first idler rollers are arranged in the other side frame. Driving force for conveying articles is given to the first idler rollers only. The fact that first idler rollers and second idler rollers are separately arranged at opposite sides assures that the first and second idler rollers are of short and light construction.

Abstract: Unit cells and separator elements are stacked in layers, thus constituting a stacked structure of a fuel cell. A first segment channel, which is bored through the peripheral region of each separator element, communicates with a second segment channel formed in a cylindrical seal member which is joined to each two adjacent separator elements. Thus, manifolds for the intake and exhaust of a fuel gas and an oxidant gas are defined. The cylindrical seal member includes a pair of ring-shaped metal members joined to each two adjacent separator elements and a ring-shaped insulating member interposed between the metal members. Thus, the gases in the manifolds can be prevented from leaking out, and the adjacent separator elements are insulated from one another.