Abstract: A delay gate is provided within a control unit to delay the reset signal by a predetermined period of time to monitor the time at which the reset signal passes through the busline. If the busline length exceeds a prescribed length, then an LED is turned on. Or a resistance proportional to the length of a duplex bus signal line is connected to each connecting portion, a reference resistance is provided internally of the control unit and one of the duplex signal buslines of the connecting portion is grounded while the other is connected through the reference resistance to a reference power supply to compare the potential difference between the reference resistance and the connecting point of the duplex signal busline with a reference signal so that, when the busline length exceeds a prescribed value, the LED is turned on.

Abstract: A delay gate is provided within a control unit to delay the reset signal by a predetermined period of time to monitor the time at which the reset signal passes through the busline. If the busline length exceeds a prescribed length, then an LED is turned on. Or a resistance proportional to the length of a duplex bus signal line is connected to each connecting portion, a reference resistance is provided internally of the control unit and one of the duplex signal buslines of the connecting portion is grounded while the other is connected through the reference resistance to a reference power supply to compare the potential difference between the reference resistance and the connecting point of the duplex signal busline with a reference signal so that, when the busline length exceeds a prescribed value, the LED is turned on.

Abstract: A signal which requires an interruption of execution of program instructions stored in a memory, is produced. The program instructions include an entry point instruction at an entry point to which a branch instruction transfers control. An instruction decoder is operatively coupled to the memory and receives the program instructions in sequence. A preceding branch instruction is coupled to the decoder and is arranged to store a signal which is applied from the decoder and which indicates whether or not the program instruction decoded by the decoder is a branch instruction. The instruction decoder further receives the signal from the indicator. The instruction decoder produces the first mentioned signal when receiving the entry point instruction which indicates that control has been transferred to a new program flow, if the signal indicates that the program instruction decoded by the decoder is not a branch instruction.

Abstract: In a computer in which an instruction is prefetched in a buffer, a prefetching queue control system includes a memory for prestoring an instruction sequence which is to be executed for a time interval before an instruction at a destination of a branch is supplied when branching occurs, and a controller for transferring the instruction sequence to the buffer and executing the transferred instruction sequence until the instruction at the destination of the branch is supplied.