Patents by Inventor Toshio Miyatake
Toshio Miyatake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7432628Abstract: A generator and a method of manufacturing the generator, which can suppress a lowering of tension of a bind ring caused by an initial deformation during assembly and changes with the lapse of time during long-term operation, and can prevent a lowering of the support function. The generator includes a coil assembled in a groove formed in an iron core of a rotor and a bind ring for fixing a coil end of the coil, which is projected outward of the iron core, to a coil support. A restraint member is disposed on at least one of opposite axial ends of the bind ring to restrain the relevant end from deforming.Type: GrantFiled: November 10, 2005Date of Patent: October 7, 2008Assignee: Hitachi, Ltd.Inventors: Toshio Miyatake, Juichi Enyama
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Publication number: 20060097606Abstract: A generator and a method of manufacturing the generator, which can suppress a lowering of tension of a bind ring caused by an initial deformation during assembly and changes with the lapse of time during long-term operation, and can prevent a lowering of the support function. The generator includes a coil assembled in a groove formed in an iron core of a rotor and a bind ring for fixing a coil end of the coil, which is projected outward of the iron core, to a coil support. A restraint member is disposed on at least one of opposite axial ends of the bind ring to restrain the relevant end from deforming.Type: ApplicationFiled: November 10, 2005Publication date: May 11, 2006Inventors: Toshio Miyatake, Juichi Enyama
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Patent number: 6977514Abstract: A probe structure is provided in which secondary electrodes of a main base material and probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, and an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.Type: GrantFiled: July 24, 2003Date of Patent: December 20, 2005Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Tatsuya Nagata, Hiroya Shimizu, Toshio Miyatake, Hideo Miura
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Patent number: 6885208Abstract: A semiconductor device includes a quadrangular semiconductor substrate and a self test circuit formed on the semiconductor substrate. A plurality of pads are formed on the semiconductor substrate, which pads are coupled at least to the self test circuit. The semiconductor substrate includes four rectangular or square regions which each include a respective corner of the quadrangle, and at least two of the pads are respectively located on diagonally opposite ones of the regions from one another.Type: GrantFiled: August 15, 2002Date of Patent: April 26, 2005Assignee: Renesas Technology Corp.Inventors: Toshio Miyatake, Tatsuya Nagata, Hiroya Shimizu, Ryuji Kohno, Hideyuki Aoki
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Patent number: 6864568Abstract: A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.Type: GrantFiled: September 24, 2002Date of Patent: March 8, 2005Assignee: Renesas Technology Corp.Inventors: Ryuji Kohno, Hiroya Shimizu, Masatoshi Kanamaru, Atsushi Hosogane, Toshio Miyatake, Hideo Miura, Tatsuya Nagata, Yoshishige Endo, Masaaki Namba, Yuji Wada
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Patent number: 6774654Abstract: A semiconductor inspecting apparatus having a plurality of electrical connection boards arranged in the inspecting apparatus and a plurality of probes respectively provided on a plurality of beams formed on a first board of said plurality of electrical connection boards, the probes being adapted to be individually brought into contact with a plurality of electrode pads of a semiconductor device for inspection, so as to inspect the semiconductor device while establishing electrical connection therebetween. A one-end supported beam is used as each of the beams, and each of the probes is formed at a portion shifted in a rectangular direction to a center line of a longitudinal direction of the one-end supported beam.Type: GrantFiled: December 12, 2002Date of Patent: August 10, 2004Assignee: Renesas Technology Corp.Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanorr Aono, Ryuji Kohno, Toshio Miyatake, Hideyuki Aoki, Naoto Ban
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Publication number: 20040145382Abstract: A probe structure is provided in which secondary electrodes of a main base material and probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, and an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.Type: ApplicationFiled: July 24, 2003Publication date: July 29, 2004Inventors: Ryuji Kohno, Tatsuya Nagata, Hiroya Shimizu, Toshio Miyatake, Hideo Miura
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Patent number: 6614246Abstract: The invention provides a probe structure in which secondary electrodes of a main base material in which probes are formed can be electrically connected to electrodes in a substrate side even when a lot of probes are formed in a large area, so that a lot of LSIs within a wafer can be tested in one lot in a wafer test process, whereby an efficiency of the test process can be improved. In the probe structure, an interposer constituted by a high rigid material is arranged between the main base material having the probes formed therein and the substrate side, and the secondary electrodes of the main base material having the probes formed therein are electrically connected to the electrodes in the substrate side via the interposer.Type: GrantFiled: August 28, 2000Date of Patent: September 2, 2003Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Tatsuya Nagata, Hiroya Shimizu, Toshio Miyatake, Hideo Miura
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Publication number: 20030102880Abstract: A semiconductor inspecting apparatus having a plurality of electrical connection boards arranged in the inspecting apparatus and a plurality of probes respectively provided on a plurality of beams formed on a first board of said plurality of electrical connection boards, the probes being adapted to be individually brought into contact with a plurality of electrode pads of a semiconductor device for inspection, so as to inspect the semiconductor device while establishing electrical connection therebetween. A one-end supported beam is used as each of the beams, and each of the probes is formed at a portion shifted in a rectangular direction to a center line of a longitudinal direction of the one-end supported beam.Type: ApplicationFiled: December 12, 2002Publication date: June 5, 2003Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanorr Aono, Ryuji Kohno, Toshio Miyatake, Hideyuki Aoki, Naoto Ban
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Publication number: 20030047731Abstract: Realized is a semiconductor device that test can be effectively conducted by the test device even where the semiconductor device is reduced in chip size and hence pad pitch. A plurality of pads are formed on both ends of a semiconductor substrate. An input pad group is arranged at a left end side of the semiconductor device while an input/output pad groups are arranged at a right end side thereof. A BIST circuit is arranged at an upper right area of the semiconductor device, and the pads close to the BIST circuit serve as BIST exclusive pads. Because the area for arranging the pads for BIST is limited due to the increase of input pads and the like and all the pads for BIST cannot be arranged at one end of the semiconductor device, the BIST pads are separately provided in both ends of the semiconductor substrate. Those close to the BIST circuit are provided as exclusive pads while the others are as common-use pads. The pads 3a and 3b are separated to the upper and lower areas of the semiconductor device.Type: ApplicationFiled: August 15, 2002Publication date: March 13, 2003Inventors: Toshio Miyatake, Tatsuya Nagata, Hiroya Shimizu, Ryuji Kohno, Hideyuki Aoki
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Publication number: 20030015779Abstract: A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.Type: ApplicationFiled: September 24, 2002Publication date: January 23, 2003Inventors: Ryuji Kohno, Hiroya Shimizu, Masatoshi Kanamaru, Atsushi Hosogane, Toshio Miyatake, Hideo Miura, Tatsuya Nagata, Yoshishige Endo, Masaaki Namba, Yuji Wada
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Patent number: 6496023Abstract: A structure is provided such that a plural cantilevers are formed on a first board formed of silicon, probes are respectively formed on the individual cantilevers at positions each offset perpendicularly to a longitudinal center line of the cantilever, and wiring connected continuously from each probe to a secondary electrode pad portion through an insulating layer. A structure is alternatively adopted such that by using a both-ends supported beam formed of silicon as the beam, each probe is formed at a position offset toward a supported portion side of the both-ends supported beam.Type: GrantFiled: November 28, 2000Date of Patent: December 17, 2002Assignee: Hitachi, Ltd.Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanorr Aono, Ryuji Kohno, Toshio Miyatake, Hideyuki Aoki, Naoto Ban
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Patent number: 6465264Abstract: A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.Type: GrantFiled: September 1, 2000Date of Patent: October 15, 2002Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Hiroya Shimizu, Masatoshi Kanamaru, Atsushi Hosogane, Toshio Miyatake, Hideo Miura, Tatsuya Nagata, Yoshishige Endo, Masaaki Namba, Yuji Wada