Patents by Inventor Toshio Mukunoki
Toshio Mukunoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120268995Abstract: A memory cell array including non-volatile memory cells is divided into a first block including a non-volatile memory cell for accumulating a degradation over time and a second block including a non-volatile memory cell for storing data. A word line select circuit and a bit line select circuit select a first word line and a first bit line connected to the second block to access the non-volatile memory cell for storing data of the second block, and selects a second word line or a second bit line connected to the first block to apply a stress voltage to the non-volatile memory cell for accumulating the degradation over time of the first block, thereby automatically detecting ambient temperature and storing accumulated stress.Type: ApplicationFiled: June 27, 2012Publication date: October 25, 2012Applicant: Panasonic CorporationInventors: Akira SUGIMOTO, Satoshi Mishima, Masahiro Toki, Kazuyuki Kouno, Hirohito Kikukawa, Toshio Mukunoki
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Publication number: 20100329019Abstract: When data is read from a memory cell of a top array block to a bit line, a switching device is closed so that the data is stored in the form of electrical charges at a bit line of a bottom array block. The switching device at a top array side is opened to drive a sense amplifier, and thus, the data read from the memory cell and retained at the bit line of the bottom array block is output to the outside. While the data is output in the above-described manner, a potential of the bit line of the top array block can be precharged to start a next read operation.Type: ApplicationFiled: September 2, 2010Publication date: December 30, 2010Applicant: Panasonic CorporationInventor: Toshio MUKUNOKI
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Publication number: 20090323427Abstract: A semiconductor memory device is provided which can achieve high performance, such as an improvement in reliability, an improvement in yield, and the like, without increasing the chip area. The semiconductor memory device is a non-volatile semiconductor memory device operable to program and erase data, and hold the data in the absence of a supplied voltage, comprising a memory cell including a first charge localized portion and a second charge localized portion each operable to store static charge corresponding to the data. The second charge localized portion stores static charge corresponding to static charge which should be stored in the first charge localized portion, thereby serving as a backup to the first charge localized portion.Type: ApplicationFiled: September 8, 2009Publication date: December 31, 2009Applicant: Panasonic CorporationInventor: Toshio MUKUNOKI
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Patent number: 7602638Abstract: A semiconductor memory device is provided which can achieve high performance, such as an improvement in reliability, an improvement in yield, and the like, without increasing the chip area. The semiconductor memory device is a non-volatile semiconductor memory device operable to program and erase data, and hold the data in the absence of a supplied voltage, comprising a memory cell including a first charge localized portion and a second charge localized portion each operable to store static charge corresponding to the data. The second charge localized portion stores static charge corresponding to static charge which should be stored in the first charge localized portion, thereby serving as a backup to the first charge localized portion.Type: GrantFiled: April 6, 2006Date of Patent: October 13, 2009Assignee: Panasonic CorporationInventor: Toshio Mukunoki
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Patent number: 7532519Abstract: A semiconductor memory device which is highly reliable, is operable at a low voltage and a high speed, and is produced at a high production yield is provided. A nonvolatile semiconductor memory device capable of reading and erasing data and holding the data even while no voltage is supplied comprises a plurality of memory cells each including a plurality of local charge portions each capable of storing a static charge corresponding to the data. Either two of the local charge portions store the charges in a complementary state.Type: GrantFiled: January 9, 2008Date of Patent: May 12, 2009Assignee: Panasonic CorporationInventor: Toshio Mukunoki
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Publication number: 20080137434Abstract: A semiconductor memory device which is highly reliable, is operable at a low voltage and a high speed, and is produced at a high production yield is provided. A nonvolatile semiconductor memory device capable of reading and erasing data and holding the data even while no voltage is supplied comprises a plurality of memory cells each including a plurality of local charge portions each capable of storing a static charge corresponding to the data. Either two of the local charge portions store the charges in a complementary state.Type: ApplicationFiled: January 9, 2008Publication date: June 12, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Toshio Mukunoki
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Patent number: 7333368Abstract: A semiconductor memory device which is highly reliable, is operable at a low voltage and a high speed, and is produced at a high production yield is provided. A nonvolatile semiconductor memory device capable of reading and erasing data and holding the data even while no voltage is supplied comprises a plurality of memory cells each including a plurality of local charge portions each capable of storing a static charge corresponding to the data. Either two of the local charge portions store the charges in a complementary state.Type: GrantFiled: April 6, 2006Date of Patent: February 19, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Toshio Mukunoki
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Patent number: 7330374Abstract: To set a threshold of a reference cell in short time in a semiconductor memory device using a variable threshold type nonvolatile memory cell as a reference current/voltage generating unit, a memory cell which keeps an initial state during an inspection process without performing write/erase operations is provided in an area of a memory cell storing data, and Vt setting of a reference cell is performed while the verification of the reference cell is performed on the basis of the memory cell which keeps the initial state during the inspection process.Type: GrantFiled: April 12, 2006Date of Patent: February 12, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Toshio Mukunoki
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Publication number: 20060258100Abstract: A semiconductor memory device is provided which can achieve high performance, such as an improvement in reliability, an improvement in yield, and the like, without increasing the chip area. The semiconductor memory device is a non-volatile semiconductor memory device operable to program and erase data, and hold the data in the absence of a supplied voltage, comprising a memory cell including a first charge localized portion and a second charge localized portion each operable to store static charge corresponding to the data. The second charge localized portion stores static charge corresponding to static charge which should be stored in the first charge localized portion, thereby serving as a backup to the first charge localized portion.Type: ApplicationFiled: April 6, 2006Publication date: November 16, 2006Inventor: Toshio Mukunoki
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Publication number: 20060250841Abstract: A semiconductor memory device which is highly reliable, is operable at a low voltage and a high speed, and is produced at a high production yield is provided. A nonvolatile semiconductor memory device capable of reading and erasing data and holding the data even while no voltage is supplied comprises a plurality of memory cells each including a plurality of local charge portions each capable of storing a static charge corresponding to the data. Either two of the local charge portions store the charges in a complementary state.Type: ApplicationFiled: April 6, 2006Publication date: November 9, 2006Inventor: Toshio Mukunoki
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Publication number: 20060239093Abstract: To set a threshold of a reference cell in short time in a semiconductor memory device using a variable threshold type nonvolatile memory cell as a reference current/voltage generating unit, a memory cell which keeps an initial state during an inspection process without performing write/erase operations is provided in an area of a memory cell storing data, and Vt setting of a reference cell is performed while the verification of the reference cell is performed on the basis of the memory cell which keeps the initial state during the inspection process.Type: ApplicationFiled: April 12, 2006Publication date: October 26, 2006Inventor: Toshio Mukunoki
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Patent number: 7075839Abstract: A memory cell array includes a memory cell region composed of memory cells and a sample cell region composed of word line sample cells and bit line sample cells. The word line sample cell and the bit line sample cell are formed so that by a voltage applied to word lines and bit lines, charge transfer from the floating gate electrode occurs more easily than the memory cell.Type: GrantFiled: April 12, 2004Date of Patent: July 11, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshio Mukunoki, Akira Sugimoto, Takao Ozeki
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Publication number: 20040208071Abstract: A memory cell array includes a memory cell region composed of memory cells and a sample cell region composed of word line sample cells and bit line sample cells. The word line sample cell and the bit line sample cell are formed so that by a voltage applied to word lines and bit lines, charge transfer from the floating gate electrode occurs more easily than the memory cell.Type: ApplicationFiled: April 12, 2004Publication date: October 21, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toshio Mukunoki, Akira Sugimoto, Takao Ozeki
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Patent number: 6067265Abstract: A reference potential generator is constituted of two signal lines 21 and 22; a charge supplier to supply charge to signal lines 21 and 22; connectors 24a and 24b connecting the charge supplier 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a connector 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.Type: GrantFiled: June 2, 1999Date of Patent: May 23, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshio Mukunoki, Hiroshige Hirano, George Nakane, Tetsuji Nakakuma, Tatsumi Sumi, Nobuyuki Moriwaki
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Patent number: 5953277Abstract: A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying circuit to supply charge to signal lines 21 and 22; a first connection circiut 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.Type: GrantFiled: March 10, 1998Date of Patent: September 14, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshio Mukunoki, Hiroshige Hirano, George Nakane, Tetsuji Nakakuma, Tatsumi Sumi, Nobuyuki Moriwaki
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Patent number: 5828615Abstract: A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying means to supply charge to signal lines 21 and 22; a first connection circuit 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.Type: GrantFiled: January 8, 1997Date of Patent: October 27, 1998Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshio Mukunoki, Hiroshige Hirano, George Nakane, Tetsuji Nakakuma, Tatsumi Sumi, Nobuyuki Moriwaki
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Patent number: 5546342Abstract: The life of a semiconductor memory device can be prolonged by using a plurality of memory cells and decreasing the stress applied to the dielectric film of the memory cells storing a data value "1." This is achieved in the present invention by decreasing the number of rewritings required to retain stored data. Specifically, the present invention utilizes a reverse and rewrite means to reverse and rewrite data back into memory cells after being read, memory means for memorizing a signal indicating whether the currently stored data is in a reversed state, and judging means for judging whether the data should be reversely output.Type: GrantFiled: October 13, 1994Date of Patent: August 13, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: George Nakane, Toshio Mukunoki, Nobuyuki Moriwaki, Tatsumi Sumi, Hiroshige Hirano, Tetsuji Nakakuma
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Patent number: 5523974Abstract: A semiconductor memory device comprises a main memory cell, a redundant memory cell, a redundant address data cell comprising a non-volatile memory which electrically memorizes an address of a redundant memory cell which replaced a failed memory cell in the main memory cell, a control circuit 15 and a redundant memory cell selecting circuit 16. The redundant memory cell selecting circuit serves to hold first address data which has been read from the redundant address data cell, and to compare the first address data with second address data for a read or write operation which is input via the control circuit and thereby select the main memory cell or the redundant memory cell.Type: GrantFiled: November 21, 1994Date of Patent: June 4, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshige Hirano, George Nakane, Tetsuji Nakakuma, Nobuyuki Moriwaki, Toshio Mukunoki, Tatsumi Sumi
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Patent number: 5515312Abstract: A semiconductor memory device comprising a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to each of the bit lines, the word line and the cell plate electrode, and a prevention means that permits only a predetermined number of readouts of data stored in the memory cell, after which the data is destroyed and is not retrieved with subsequent readout attempts.Type: GrantFiled: October 13, 1994Date of Patent: May 7, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsuji Nakakuma, Tatsumi Sumi, Hiroshige Hirano, George Nakane, Nobuyuki Moriwaki, Toshio Mukunoki