Patents by Inventor Toshio Ninomiya
Toshio Ninomiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240116031Abstract: An object of the present invention is to provide a catalyst that enables production of an unsaturated carboxylic acid and/or unsaturated carboxylic acid ester represented by methyl methacrylate with high selectivity. The object is achieved by a catalyst including: one or more elements selected from boron, magnesium, zirconium, hafnium, and titanium; one or more elements selected from alkali metal elements; and silica; the catalyst having a peak height ratio I2/I1 of 0 to 1.2, wherein I1 represents the peak height at 417±10 cm?1, and I2 represents the peak height at 1050±10 cm?1, as obtained by Raman spectroscopy.Type: ApplicationFiled: November 30, 2023Publication date: April 11, 2024Applicant: Mitsubishi Chemical CorporationInventors: Akio Hayashi, Yuuki Tsujimoto, Toshio Hasegawa, Kazufumi Nishida, Masaya Fujisue, Wataru Ninomiya
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Patent number: 10338997Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.Type: GrantFiled: May 17, 2018Date of Patent: July 2, 2019Assignee: Micron Technology, Inc.Inventors: Chiaki Dono, Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo
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Publication number: 20180293128Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the fist external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.Type: ApplicationFiled: May 17, 2018Publication date: October 11, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Chiaki Dono, Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo
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Patent number: 9983925Abstract: A control circuit receives the mode signals supplied from a mode register and a read enable signal READ supplied from a control logic circuit, which activates enable signals EN1 to EN3 based on the mode signals and read enable signal. For example, the read enable signal READ is activated when a read command is issued from the controller. One mode signal can indicate an operation mode in which a multi-purpose register is used, and another mode signal can indicate an operation mode in which the data bus inversion function is used. When a data masking operation is disabled and an error check operation is enabled, the mode register activates a protection signal SEL. When the data masking operation is enabled or the error check operation is disabled, the protection signal SEL is deactivated. The operation of a deserializer is controlled by clock signals and the protection signal SEL.Type: GrantFiled: April 3, 2015Date of Patent: May 29, 2018Assignee: Micron Technology, Inc.Inventors: Chiaki Dono, Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo
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Patent number: 9612490Abstract: The present invention provides a liquid crystal display having the advantage of higher resolution and lower power consumption while having high transmittance. The present invention is a liquid crystal display provided with a first substrate, a second substrate and a horizontal orientation-type liquid crystal layer. The first substrate includes a plurality of source bus lines, a plurality of gate bus lines, a pixel electrode, a first common electrode, a first interlayer insulation film on the plurality of source bus lines, a first conductive layer on the first interlayer insulation film, a second interlayer insulation film on the first conductive layer and a second conductive layer on the second interlayer insulation film. The first common electrode includes a plurality of first linear portions having a linear shape. The pixel electrode includes one or more second linear portions. The plurality of first linear portions and one or more second linear portions are alternately disposed.Type: GrantFiled: December 20, 2013Date of Patent: April 4, 2017Assignee: SHARP KABUSHIKI KAISHAInventors: Hiroyuki Moriwaki, Toshio Ninomiya, Kazutaka Hanaoka
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Publication number: 20160034340Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit, The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and as data bus invasion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.Type: ApplicationFiled: April 3, 2015Publication date: February 4, 2016Inventors: CHIAKI DONO, Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo
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Publication number: 20150346564Abstract: The present invention provides a liquid crystal display having the advantage of higher resolution and lower power consumption while having high transmittance. The present invention is a liquid crystal display provided with a first substrate, a second substrate and a horizontal orientation-type liquid crystal layer. The first substrate includes a plurality of source bus lines, a plurality of gate bus lines, a pixel electrode, a first common electrode, a first interlayer insulation film on the plurality of source bus lines, a first conductive layer on the first interlayer insulation film, a second interlayer insulation film on the first conductive layer and a second conductive layer on the second interlayer insulation film. The first common electrode includes a plurality of first linear portions having a linear shape. The pixel electrode includes one or more second linear portions. The plurality of first linear portions and one or more second linear portions are alternately disposed.Type: ApplicationFiled: December 20, 2013Publication date: December 3, 2015Inventors: Hiroyuki MORIWAKI, Toshio NINOMIYA, Kazutaka HANAOKA
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Patent number: 9183949Abstract: A device includes a decoder, a selector, and a plurality of registers. The decoder is configured to generate a plurality of test signals. The selector is coupled to the decoder. The selector is configured to sequentially select a test signal from the plurality of test signals and to sequentially output the test signal selected. The plurality of registers is coupled in series to each other. The plurality of registers includes a first stage register. The first stage register is coupled to the selector to sequentially receive the test signal from the selector.Type: GrantFiled: December 13, 2011Date of Patent: November 10, 2015Assignee: PS4 Luxco S.a.r.l.Inventors: Hiromasa Noda, Toshio Ninomiya
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Publication number: 20120158347Abstract: A device includes a decoder, a selector, and a plurality of registers. The decoder is configured to generate a plurality of test signals. The selector is coupled to the decoder. The selector is configured to sequentially select a test signal from the plurality of test signals and to sequentially output the test signal selected. The plurality of registers is coupled in series to each other. The plurality of registers includes a first stage register. The first stage register is coupled to the selector to sequentially receive the test signal from the selector.Type: ApplicationFiled: December 13, 2011Publication date: June 21, 2012Inventors: Hiromasa NODA, Toshio Ninomiya
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Patent number: 8137941Abstract: A chondroitin polymerase having such properties that it transfers GlcUA and GalNAc alternately to a non-reduced terminal of a sugar chain from a GlcUA donor and a GalNAc donor, respectively, and the like; and a process for producing the chondroitin polymerase.Type: GrantFiled: August 10, 2009Date of Patent: March 20, 2012Assignee: Seikagaku CorporationInventors: Toshio Ninomiya, Nobuo Sugiura, Koji Kimata
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Patent number: 7723092Abstract: A chondroitin polymerase having such properties that it transfers GlcUA and GalNAc alternately to a non-reduced terminal of a sugar chain from a GlcUA donor and a GalNAc donor, respectively, and the like; and a process for producing the chondroitin polymerase.Type: GrantFiled: July 12, 2006Date of Patent: May 25, 2010Assignee: Seikagaku CorporationInventors: Toshio Ninomiya, Nobuo Sugiura, Koji Kimata
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Publication number: 20090305357Abstract: A chondroitin polymerase having such properties that it transfers GlcUA and GalNAc alternately to a non-reduced terminal of a sugar chain from a GlcUA donor and a GalNAc donor, respectively, and the like; and a process for producing the chondroitin polymerase.Type: ApplicationFiled: August 10, 2009Publication date: December 10, 2009Applicant: Seikagaku Kogyo Kabushiki KaishaInventors: Toshio NINOMIYA, Nobuo Sugiura, Koji Kimata
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Patent number: 7598068Abstract: A chondroitin polymerase having such properties that it transfers GlcUA and GalNAc alternately to a non-reduced terminal of a sugar chain from a GlcUA donor and a GalNAc donor, respectively, and the like; and a process for producing the chondroitin polymerase.Type: GrantFiled: August 12, 2002Date of Patent: October 6, 2009Assignee: Seikagaku CorporationInventors: Toshio Ninomiya, Nobuo Sugiura, Koji Kimata
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Publication number: 20070015249Abstract: A chondroitin polymerase having such properties that it transfers GlcUA and GalNAc alternately to a non-reduced terminal of a sugar chain from a GlcUA donor and a GalNAc donor, respectively, and the like; and a process for producing the chondroitin polymerase.Type: ApplicationFiled: July 12, 2006Publication date: January 18, 2007Applicant: Seikagaku CorporationInventors: Toshio Ninomiya, Nobuo Sugiura, Koji Kimata
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Publication number: 20030109693Abstract: A chondroitin polymerase having such properties that it transfers GlcUA and GalNAc alternately to a non-reduced terminal of a sugar chain from a GlcUA donor and a GalNAc donor, respectively, and the like; and a process for producing the chondroitin polymerase.Type: ApplicationFiled: August 12, 2002Publication date: June 12, 2003Applicant: Seikagaku CorporationInventors: Toshio Ninomiya, Nobuo Sugiura, Koji Kimata
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Patent number: 5228694Abstract: An iron golf club head having a sole and a hosel molded integrally as a frame from a metallic material, a core portion disposed in an upper part above the sole and the outer periphery of the core portion and the outer periphery of the frame except for the sole are covered with a fiber-reinforced resin and a weight having a greater specific gravity than the metallic material of the frame disposed between the sole and the core portion. The weight consists of a mass of 92 to 98 wt. % of powdery tungsten mixed in a polyamide resin.Type: GrantFiled: February 28, 1992Date of Patent: July 20, 1993Assignee: The Yokohama Rubber Co., Ltd.Inventors: Takaharu Okumoto, Toshio Ninomiya, Tetsuo Hayashi, Kazuo Kawada
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Patent number: 5158289Abstract: A golf club wherein at least the surface of the face of a club head made of fiber-reinforced plastic or wood or the surface of a club shaft made of fiber-reinforced plastic is covered with a cured coating layer of a silicone-modified synthetic resin.Type: GrantFiled: August 2, 1991Date of Patent: October 27, 1992Assignee: The Yokohama Rubber Co., Ltd.Inventors: Takaharu Okumoto, Tadashi Hayashida, Tetsuo Hayashi, Toshio Ninomiya
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Patent number: D664226Type: GrantFiled: July 14, 2011Date of Patent: July 24, 2012Assignee: Mitsubishi Rayon Co., Ltd.Inventors: Akinari Itou, Hikaru Shiraishi, Toshio Ninomiya, Tsutomu Ibuki
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Patent number: D664620Type: GrantFiled: July 14, 2011Date of Patent: July 31, 2012Assignee: Mistubishi Rayon Co., Ltd.Inventors: Akinari Itou, Hikaru Shiraishi, Toshio Ninomiya, Tsutomu Ibuki
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Patent number: D699801Type: GrantFiled: August 31, 2012Date of Patent: February 18, 2014Assignee: Mitsubishi Rayon Co., Ltd.Inventors: Akinari Ito, Kouji Shiga, Toshio Ninomiya