Patents by Inventor Toshio Oguma

Toshio Oguma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5911061
    Abstract: A program data creating method and apparatus for use with programmable devices in a logic emulation system provides high-speed logic emulation of an LSI for logic and function verification. The logic data defining the logic circuits of the LSI is divided into a plurality of unit blocks in a layout analogous to the floor plan represented by floor plan information for the LSI. The unit blocks are allocated to the programmable devices automatically. The names of the signals defined within the design data regarding the LSI are made to correspond with the names of the signals in effect when the design data is deployed within the programmable devices, after optimization of the logic. This allows the program data for the programmable devices to be created and corrected using the signal names as set forth in the design data.
    Type: Grant
    Filed: August 6, 1996
    Date of Patent: June 8, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuya Tochio, Osamu Tada, Toshio Oguma, Kazunobu Morimoto, Mototsugu Fujii
  • Patent number: 5875116
    Abstract: The electronic circuits of a large-scale ASIC or logic device are assigned to a plurality of programmable chips with logic block division that enables the finished circuits to operate at appropriate timings. A logic division processing unit divides the electronic circuits into a plurality of groups for automatic assignment to a plurality of programmable chips. A checking unit determines whether the designated logic blocks are accommodated in one programmable chip, and a division processing unit determines which logic blocks are to be assigned and the order of assignment priorities when the designated logic blocks are not all accommodated in the same programmable chip.
    Type: Grant
    Filed: January 18, 1996
    Date of Patent: February 23, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Oguma, Osamu Tada
  • Patent number: 5701443
    Abstract: A logic simulation system for simulating a quality of logic description of a tested electric circuit includes a storage for storing execution results of logic simulation which was conducted for the electric circuit in the past and for which operations of the circuit have been confirmed, logic description to be tested for the electric circuit, and test data of the logic description to be tested. Logic simulation is conducted according to the test data and the logic description to be tested. Results of the logic simulation are compared with the past logic simulation results of operation by correcting time values according to a predetermined rule so as to simulate quality of the logic description, thereby outputting quality of the logic description in a visible form.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: December 23, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Oguma, Yoshinobu Okazaki, Osamu Tada, Shigeki Yokotani
  • Patent number: 5561281
    Abstract: Each of multiple cash cassettes is provided with a light-emission type push-button switch capable of indicating the operation state of the cash cassette and the need to exchange the cash cassette. By depressing the push-button switch, the associated cash cassette is separated from the cash transaction operation under the control of a CPU. When a customer is in front of a transaction apparatus or while a cash transaction is being carried out, a lamp of the push-button switch associated with the cash cassette, from which banknotes may be taken out in a subsequent dispensing operation, is flickered at a cycle of 1 second. When banknotes are replenished in the cash cassette, the banknotes can be replenished without suspending the operation of the apparatus, and the operation efficiency and operability of the apparatus can be enhanced.
    Type: Grant
    Filed: November 2, 1994
    Date of Patent: October 1, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Eda, Toshio Oguma