Patents by Inventor Toshio Ohshima
Toshio Ohshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Method for forming quantum dot, and quantum semiconductor device and method for fabricating the same
Patent number: 7755080Abstract: The method for forming a quantum dot according to the present invention comprises the step of forming an oxide in a dot-shape on the surface of a semiconductor substrate 10, the step of removing the oxide to form a concavity 16 in the position from which the oxide has been removed, and the step of growing a semiconductor layer 18 on the semiconductor substrate with the concavity formed in to form a quantum dot 20 of the semiconductor layer in the concavity. The concavity is formed in the semiconductor substrate by forming the oxide dot in the surface of the semiconductor substrate and removing the oxide, whereby the concavity can be formed precisely in a prescribed position and in a prescribed size. The quantum dot is grown in such a concavity, whereby the quantum dot can have good quality and can be formed in a prescribed position and in a prescribed size.Type: GrantFiled: October 30, 2007Date of Patent: July 13, 2010Assignee: Fujitsu LimitedInventors: Hai-Zhi Song, Toshio Ohshima -
Method for forming quantum dot, and quantum semiconductor device and method for fabricating the same
Publication number: 20080067498Abstract: The method for forming a quantum dot according to the present invention comprises the step of forming an oxide in a dot-shape on the surface of a semiconductor substrate 10, the step of removing the oxide to form a concavity 16 in the position from which the oxide has been removed, and the step of growing a semiconductor layer 18 on the semiconductor substrate with the concavity formed in to form a quantum dot 20 of the semiconductor layer in the concavity. The concavity is formed in the semiconductor substrate by forming the oxide dot in the surface of the semiconductor substrate and removing the oxide, whereby the concavity can be formed precisely in a prescribed position and in a prescribed size. The quantum dot is grown in such a concavity, whereby the quantum dot can have good quality and can be formed in a prescribed position and in a prescribed size.Type: ApplicationFiled: October 30, 2007Publication date: March 20, 2008Applicant: FUJITSU LIMITEDInventors: Hai-Zhi Song, Toshio Ohshima -
Method for forming quantum dot, and quantum semiconductor device and method for fabricating the same
Patent number: 7307030Abstract: The method for forming a quantum dot according to the present invention comprises the step of forming an oxide in a dot-shape on the surface of a semiconductor substrate 10, the step of removing the oxide to form a concavity 16 in the position from which the oxide has been removed, and the step of growing a semiconductor layer 18 on the semiconductor substrate with the concavity formed in to form a quantum dot 20 of the semiconductor layer in the concavity. The concavity is formed in the semiconductor substrate by forming the oxide dot in the surface of the semiconductor substrate and removing the oxide, whereby the concavity can be formed precisely in a prescribed position and in a prescribed size. The quantum dot is grown in such a concavity, whereby the quantum dot can have good quality and can be formed in a prescribed position and in a prescribed size.Type: GrantFiled: November 19, 2004Date of Patent: December 11, 2007Assignee: Fujitsu LimitedInventors: Hai-Zhi Song, Toshio Ohshima -
Method for forming quantum dot, and quantum semiconductor device and method for fabricating the same
Publication number: 20050173695Abstract: The method for forming a quantum dot according to the present invention comprises the step of forming an oxide in a dot-shape on the surface of a semiconductor substrate 10, the step of removing the oxide to form a concavity 16 in the position from which the oxide has been removed, and the step of growing a semiconductor layer 18 on the semiconductor substrate with the concavity formed in to form a quantum dot 20 of the semiconductor layer in the concavity. The concavity is formed in the semiconductor substrate by forming the oxide dot in the surface of the semiconductor substrate and removing the oxide, whereby the concavity can be formed precisely in a prescribed position and in a prescribed size. The quantum dot is grown in such a concavity, whereby the quantum dot can have good quality and can be formed in a prescribed position and in a prescribed size.Type: ApplicationFiled: November 19, 2004Publication date: August 11, 2005Inventors: Hai-Zhi Song, Toshio Ohshima -
Patent number: 6770916Abstract: The quantum circuit device comprises: an asymmetrical coupled quantum dot of a main quantum dot 3a and an operational quantum dot 3b of a smaller size than the main quantum dot 3c; an asymmetrical coupled quantum dot of a main quantum dot 3c arranged at a distance which does not permit to substantially tunnel from the main quantum dot 3a, and an operation quantum dot 3d having a smaller size than the main quantum dot 3c and arranged at a distance which permits tunneling from the operational quantum dot 3b; and a laser device for applying to the asymmetrical coupled quantum dots a laser beam of a wavelength which resonates an inter-level energy the asymmetrical coupled quantum dots. In the sleep state, electron is present at the ground state of the main quantum dot, where no exchange interaction takes place, and in an operation, the electron is transited to an excited state of the operational quantum dot, whereby the operation is made by the exchange interactions between the adjacent operational quantum dots.Type: GrantFiled: March 19, 2002Date of Patent: August 3, 2004Assignee: Fujitsu LimitedInventor: Toshio Ohshima
-
Publication number: 20030052317Abstract: The quantum circuit device comprises: an asymmetrical coupled quantum dot of a main quantum dot 3a and an operational quantum dot 3b of a smaller size than the main quantum dot 3c; an asymmetrical coupled quantum dot of a main quantum dot 3c arranged at a distance which does not permit to substantially tunnel from the main quantum dot 3a, and an operation quantum dot 3d having a smaller size than the main quantum dot 3c and arranged at a distance which permits tunneling from the operational quantum dot 3b; and a laser device for applying to the asymmetrical coupled quantum dots a laser beam of a wavelength which resonates an inter-level energy the asymmetrical coupled quantum dots. In the sleep state, electron is present at the ground state of the main quantum dot, where no exchange interaction takes place, and in an operation, the electron is transited to an excited state of the operational quantum dot, whereby the operation is made by the exchange interactions between the adjacent operational quantum dots.Type: ApplicationFiled: March 19, 2002Publication date: March 20, 2003Applicant: FUJITSU LIMITEDInventor: Toshio Ohshima
-
Patent number: 6194737Abstract: This invention is characterized in that a load resistor is constituted of a tunneling junction element(12), and a single-electron tunneling junction element(10) and the tunneling junction element(12) for load resistor are laminated to design a phase-locked circuit compact. Further, the load resistor(12) is comprised of a plurality of laminated tunneling junctions for load resistor so that the load resistor can have the proper resistance. A DC bias voltage is applied to the electrode(37) of the tunneling junction element for load resistor, and an AC pump voltage to one electrode(20) of the single-electron tunneling junction element. In the case of a plurality of phase-locked circuit gates, one electrodes of the single-electron tunneling junction elements are designed into a common electrode to which the AC pump voltage is applied, and the other electrodes are formed apart from one another two-dimensionally.Type: GrantFiled: July 30, 1998Date of Patent: February 27, 2001Assignee: Fujitsu LimitedInventor: Toshio Ohshima
-
Patent number: 5856681Abstract: The present invention relates to a semiconductor device in which an electric resistance in a carrier path is modulated by changing a voltage applied to the carrier path. The semiconductor device is provided with a semiconductor layer in which conductive particles are dispersed to scatter carriers, a first electrode, and a second electrode for passing the carriers through the semiconductor device in cooperation with the first electrode.Type: GrantFiled: December 23, 1996Date of Patent: January 5, 1999Assignee: Fujitsu LimitedInventor: Toshio Ohshima
-
Patent number: 5731717Abstract: A single-electron tunneling (SET) element used as a logic or memory element includes at least one tunneling junction with a minute metal-insulator-metal sandwich structure, and a biasing power source which is connected in series to the at least one tunneling junction and whose ON/OFF operation is controlled by an external control input. SET oscillations are generated in the at least one tunneling junction and the generated oscillations are phase-locked to subharmonics of a pump signal supplied from an AC power source, to thus exhibit a plurality of stable phase states. Also, a plurality of gates, each including the SET element, are constituted in the form of a logic network to realize a predetermined logic operation in a computer. In the logic network, an input signal with a frequency half that of the pump signal is continually applied to a specified gate among the plurality of gates, while the biasing power sources of all of the gates are kept in ON state.Type: GrantFiled: April 5, 1996Date of Patent: March 24, 1998Assignee: Fujitsu LimitedInventors: Toshio Ohshima, Richard A. Kiehl
-
Patent number: 5214297Abstract: A high-speed semiconductor device comprising emitter potential barrier layer disposed between an emitter layer and a base layer, a collector layer, and a collector potential barrier layer disposed between the base layer and the collector layer. The collector potential barrier layer has a structure having a barrier height changing from a high level to a low level along the direction from the base layer to the collector layer, whereby, even when no bias voltage is applied between the collector layer and the emitter layer, a collector current can flow through the device.Type: GrantFiled: July 28, 1992Date of Patent: May 25, 1993Assignee: Fujitsu LimitedInventors: Kenichi Imamura, Naoki Yokoyama, Toshio Ohshima
-
Patent number: 5198879Abstract: A heterojunction semiconductor device utilizing a quantum-mechanical effect comprises a first compound semiconductor (e.g., AlGaAs) layer and a second compound semiconductor (e.g., GaAs) layer having an electron affinity different from that of the first semiconductor layer, and the first and second compound semiconductor layers forming a heterojunction interface therebetween, the first layer having an energy at the conduction band bottom thereof higher than that of the second layer and doped with donor impurities, wherein at least one concave or convex portion of the first semiconductor layer is formed at the heterojunction interface and both sides of the concave or convex portion serve as a potential well or potential barriers against electrons accumulated in the second semiconductor layer close to the vicinity of the heterojunction interface.Type: GrantFiled: March 19, 1991Date of Patent: March 30, 1993Assignee: Fujitsu LimitedInventor: Toshio Ohshima
-
Patent number: 5140252Abstract: In a method of charging secondary battery, the charging control is performed when it is detected that the secondary differential value of the detected voltage curve changes from positive value to a negative value at the point C or its near portion.Type: GrantFiled: February 28, 1991Date of Patent: August 18, 1992Assignee: Hitachi Maxell, Ltd.Inventors: Masanobu Kizu, Ryo Nagai, Toshio Ohshima, Tsunemi Ohiwa, Kozo Kajita
-
Patent number: 4996166Abstract: A heterojunction bipolar transistor includes a base layer and a wide bandgap emitter layer. A portion of the base layer is exposed, a base electrode is formed thereon and the active region of the emitter-base junction is limited inside a semiconductor body. As a result, surface recombination current generation of the peripheral region of the junction is prevented and the emitter efficiency is improved.Type: GrantFiled: January 17, 1990Date of Patent: February 26, 1991Assignee: Fujitsu LimitedInventor: Toshio Ohshima
-
Patent number: 4924283Abstract: A heterojunction bipolar transistor includes a base layer and a wide bandgap emitter layer. A portion of the base layer is exposed, a base electrode is formed thereon and the active region of the emitter-base junction is limited inside a semiconductor body. As a result, surface recombination current generation of the peripheral region of the junction is prevented and the emitter efficiency is improved.Type: GrantFiled: October 20, 1988Date of Patent: May 8, 1990Assignee: Fujitsu LimitedInventor: Toshio Ohshima
-
Patent number: 4837178Abstract: A compound semiconductor (e.g., GaAs) IC device structure includes: a compound semiconductor substrate having a semi-insulating compound surface region; an active element laminated layer formed on the surface region; an isolation region of a semi-insulating (intrinsic) compound semiconductor which is filled in a groove extending into the surface region through the laminated layer; and active elements formed in regions of the laminated layer, isolated by the filled groove.Type: GrantFiled: September 4, 1987Date of Patent: June 6, 1989Assignee: Fujitsu LimitedInventors: Toshio Ohshima, Naoki Yokoyama
-
Patent number: 4617724Abstract: When the collector, base and emitter layers of a heterojunction bipolar transistor or a tunneling hot electron transistor are vertically stacked, the thickness of the base layer is preferably small so as to increase the current gain or switching speed. A thin base layer, however, has a disadvantage in that a space of the base layer between the actual base region and the base electrode makes the base resistance too large, decreasing current gain or switching speed, or is fully depleted due to interface states, making the transistor inoperable. This disadvantage is eliminated by forming a base contact region by doping in a region in alignment with the edge of an electrode so as to remove said space, that is, the base contact region is in contact with the actual base region.Type: GrantFiled: September 30, 1985Date of Patent: October 21, 1986Assignee: Fujitsu LimitedInventors: Naoki Yokoyama, Toshio Ohshima
-
Patent number: 4542406Abstract: The horizontal sync signal contained in the video signal from a video apparatus sometimes undergoes phase jump, resulting in failure of multiplexing of audio and video signals based on the horizontal sync signal. A sync signal switching circuit is adapted to produce a modified sync signal by switching the sync signal to a local sync signal upon occurrence of the phase jump, thereby assuring the multiplexing of audio and video signals.Type: GrantFiled: December 7, 1982Date of Patent: September 17, 1985Assignees: Nippon Electric Co., Ltd., Nippon Telegraph & Telephone Public Corporation, Fujitsu LimitedInventors: Haruo Shimoyama, Toshio Ohshima, Shinobu Nomoto, Makoto Hiraoka, Toshio Hanabata