Abstract: A frequency converter circuit which multiplies a received signal which is a radio frequency signal by a locally-generated signal and extracts a signal including a frequency corresponding to a difference between the harmonic of the locally-generated signal and the frequency of the radio frequency signal, includes: a mixer section that multiplies the received signal by the locally-generated signal; a timing signal generation section that generates a timing signal synchronized with the locally-generated signal; a sample-and-hold section that samples and holds an output signal of the mixer section according to the timing signal; and a filter section that extracts, from an output signal of the sample-and-hold section, a signal component including the frequency corresponding to the difference between the harmonic of the locally-generated signal and the frequency of the radio frequency signal.

Abstract: This semiconductor memory device has an input circuit to which an external signal is connected, a program circuit which includes fuses capable of being cut, the program circuit determining the product type of the memory device by the combination of the cut fuses, and the operation of the input stage of the input circuit being controlled by the output of the program circuit. By simply cutting prescribed fuses after the end of the semiconductor manufacturing process, such things at outside elements become unnecessary, and the product type can be selected without an increase in the consumption current at the input circuit. Further, photomasks for each product type become unnecessary, mask management becomes simpler and management for different product types during the manufacturing process becomes unnecessary. Also, adjustments for production levels after manufacturing, adjustments for stock, and production control becomes easier.

Abstract: A signal voltage level conversion circuit has a configuration in which all transistors can be produced, during the semiconductor fabrication process, so that their gate-source, gate-drain, and gate-substrate voltages are within the 3v voltage tolerance range. The signal voltage level conversion circuit converts input signals with a narrow logical amplitude of 0.about.3v to output signals with a wide logical amplitude of 0.about.5v. The input signal Vin, 0.about.3v, is temporarily converted into a mediator signal Vm, approximately 3.about.5v by a mediator signal generation circuit. An output buffer circuit then converts mediator signal Vm to output signal Vout of 0.about.5v. In the mediator signal generation circuit and the output buffer circuit, application of voltage is relaxed on a plurality of transistors, so that all transistors are maintained within the 3v voltage tolerance range.

Abstract: A video signal processor comprising: a device defining a color pallet for converting a color code specifying the color of each pixel of a display picture into digital RGB color data; and a conversion system for converting the RGB color data into a luminance signal and two color-difference signals represented by analog values, wherein the conversion system includes: a memory storing digital values constituting a conversion system for converting the digital RGB color data into a luminance signal and two color-difference signals represented by digital values; and a digital-analog converter connected to the conversion system for converting the luminance signal and two color-difference signals represented by digital values into the luminance signal and two color-difference signals represented by analog values.

Abstract: An electronic memoranda device especially suitable for the retrieval of stored data with low energy consumption is provided. In the electronic memoranda device, days, times, and schedules, and the like, are stored in a data memory. At regular intervals a key portion of these stored times is compared with a key portion of a current time signal outputted from a timekeeping circuit. When the key portion of time data read out from the data memory coincides with the corresponding portion of the currently outputted timekeeping signal, the entire data stored in memory is scanned for coincidence with the complete timekeeping signal. Coincident data is outputted for display. When the initial survey of the memory indicates that no data is stored corresponding to the key current time unit provided by the timekeeping circuit, the inspection operation of the memory is interrupted until the occurrence of the next time unit wherein inspection of the memory is repeated.

Abstract: A video detecting circuit and an intercarrier sound signal generating circuit suited for implementation in an integrated circuit for use in a television receiver, comprising a video intermediate frequency amplifier including a final stage video intermediate frequency transformer, a tuning circuit coupled to the video intermediate frequency amplifier to be tuned to the video intermediate frequency for withdrawing a video intermediate frequency carrier signal, a diode connection coupled to the tuning circuit for pulsing the video intermediate frequency carrier signal, a double balanced synchronous detector responsive to the video intermediate frequency amplifier and the pulsing circuit for synchronous detecting the video intermediate frequency signal for providing a detected video signal, and a double balanced multiplier coupled to receive the primary and secondary signals at the primary and secondary windings of the video intermediate frequency transformer for evaluating the product of the primary and secondar

Abstract: An automatic fine tuning circuit in a television receiver, comprising a tuner including a voltage controlled variable reactance device constituting a tuning circuit, a video intermediate frequency amplifier for amplifying an intermediate frequency signal from the tuner, an interstage coil coupled to the video intermediate frequency amplifier, a synchronous detector having a high quality tuning characteristic of the video carrier frequency and coupled to the interstage coil for detecting the video signal through synchronous detection, a frequency discriminator having a tuning circuit coupled to the last stage of the video intermediate frequency amplifier in a direct current manner for discriminating the shift of the video carrier frequency for providing an automatic fine tuning control signal, the automatic fine tuning control signal being applied to the tuner for controlling the voltage controlled variable reactance device for the automatic fine tuning operation, a video amplifier coupled to the synchronous d

Abstract: The present disclosure relates to a receiver unit for remote controller to be employed in telecommunication apparatuses such as television sets, in which the tuning devices such as channel selecting system and/or volume for loudness can be controlled through manipulation of transmitter separately provided for the television set. The receiver unit incorporated in the television set includes a hysteresis circuit which generates a signal having two distinctive states upon receipt of fluctuating signal from the transmitter, so as to stabilize the operation of the operator in the receiver unit during the actuation thereof.