Abstract: A serial interface circuit which can adapt to various frame formats to reduce the load on a CPU. The interface circuit includes a rewritable control register used for programmably specifying a field structure to be targeted for processing out of structures of fields preceding a data field of a frame as defined by a communication protocol. The interface circuit analyzes the field structure preceding the data field according to a setting of the control register. When a destination of a received frame is determined to match an expected value, the interface circuit issues a request for the CPU to process the data field information. After a setting is made on the control register, the serial interface circuit can adapt to various formats of frames as defined by a communication protocol according to the information held there, and can also analyze a destination.

Abstract: The serial interface circuit can adapt to various frame formats readily and reduces the load on CPU owing to serial interface. The interface circuit includes a rewritable control register used for programmably specifying a field structure to be targeted for processing out of structures of fields before a data field of a frame defined by a communication protocol. The inter face circuit analyzes the field structure before the data field according to a setting of the control register. Only when a destination of a received frame is judged to match an expected value, the inter face circuit issues a request for having CPU process the data field information. After a setting is made on the control register, the serial interface circuit can readily adapt to various formats of frames defined by a communication protocol according to the information held there, and can even analyze a destination.