Patents by Inventor Toshio Oura
Toshio Oura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6738761Abstract: In an information processing system, an information storing unit stores a plurality of main information sets along with time information sets. A retrieval condition input unit inputs retrieval conditions for the main information sets. A retrieval execution unit performs a retrieval upon the main information sets along with the time information sets by using the retrieval conditions. A cell output information generating unit receives retrieved main information sets along with the time information sets and generates a number of the main information sets and a tendency of the number of the main information sets to change with respect to time for each of cells defined by the retrieval conditions. A cell output unit outputs each of the cell and displays each of the cells at a location on a matrix designated by the retrieval conditions.Type: GrantFiled: September 13, 2000Date of Patent: May 18, 2004Assignee: NEC CorporationInventor: Toshio Oura
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Patent number: 4841487Abstract: For improvement in operation speed, there is disclosed a semiconductor memory device comprising a memory cell array associated by a addressing circuit for reading out a plurality of data bits, a series of selector modules operative to decrease in number the data bits stage by stage, a temporary data storage module preserving the data bits fed from the final stage of the selector module and supplying all of the data bits to a destination, and a control circuit operative to produce an internal addressing signal for selection of the data bits, wherein the addressing circuit and the selector module except for the final stage of the selector module are supplied with the internal addressing signal for selection but the final stage of the selector module is directly supplied from the temporary data storage with a part of data bits, thereby realizing a parallel operation for reduction in time period for read-out operation.Type: GrantFiled: February 26, 1988Date of Patent: June 20, 1989Assignee: NEC CorporationInventors: Shigeki Demura, Toshio Oura
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Patent number: 4775823Abstract: According to a method for controlling an automatic door of the present invention, even when an accidental condition occurs due to some obstacle clogging a traveling lane of the door, the door can move at a high speed to its deceleration point so as to immediately enable a man to go through the door opening, while the door is prevented from colliding at a high speed against the obstacle repeatedly to make it possible to increase both the durability and safety of the door.Type: GrantFiled: December 29, 1986Date of Patent: October 4, 1988Assignee: Yoshida Kogyo K. K.Inventors: Yukio Yoshida, Akiyoshi Takimoto, Kenzo Ono, Kiyotada Nishikawa, Toshio Oura
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Patent number: 4742245Abstract: In a method for controlling an automatic door system, after a power-supply switch of the system is turned on, a door of the system initially conducts its low-speed opening/closing operation when a first human-body detection signal is inputted to the system; and then, when the door travels a distance more than a predetermined minimum door stroke, the door conducts its normal-speed opening/closing operation after completion of its traveling the predetermined minimum door stroke to enable the door to conduct its normal-speed operation within a short time after the power-supply switch is turned on.Type: GrantFiled: December 17, 1986Date of Patent: May 3, 1988Assignee: Yoshida Kogyo K. K.Inventors: Yukio Yoshida, Akiyoshi Takimoto, Kenzo Ono, Kiyotada Nishikawa, Toshio Oura
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Patent number: 4577343Abstract: Speech is synthesized by repeated readout of prestored basic speech waveforms. For varying the speech tone frequency, readout is done at a fixed rate but skipping samples sequentially stored.Type: GrantFiled: September 12, 1983Date of Patent: March 18, 1986Assignee: Nippon Electric Co. Ltd.Inventor: Toshio Oura
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Patent number: 4470113Abstract: An information processing unit, such as a central processor, microprocessor or one-chip microcomputer, which can be used as either a master unit or a slave unit yet does not require the provision of extra external terminals for control signals. The unit is provided with first and second bidirectional input/output ports and an internal bus coupled to both of the first and second input/output ports. The input/output mode of the two busses can be controlled either by an internally-generated control signal or by an externally-supplied control signal inputted to the unit. The one of the first and second control signals used for controlling the transmission modes of the input/output ports is determined in accordance with data input through one of the input/output ports and stored internally of the unit.Type: GrantFiled: January 13, 1982Date of Patent: September 4, 1984Assignee: Nippon Electric Co., Ltd.Inventor: Toshio Oura
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Patent number: 4408094Abstract: An improved output circuit for driving a loudspeaker with a single-polarity current source is disclosed. The output circuit comprises a digital to analog converter including a series circuit of a variable register and a field effect transistor for generating a variable bias potential, a plurality of current source transistors and a plurality of transfer field transistors each for selectively applying the variable bias potential to a gate of an associated current source transistor in accordance with a digital signal; a loudspeaker; and two pairs of switching transistors for alternately supplying the loudspeaker with different polarities of an output current of the digital to analog converter.Type: GrantFiled: October 16, 1980Date of Patent: October 4, 1983Assignee: Nippon Electric Co., Ltd.Inventor: Toshio Oura
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Patent number: 4318097Abstract: A pattern display apparatus in which a pattern is composed of a plurality of rectangular picture elements, picture element signals representing the picture elements are generated from a pattern generator in synchronism with a scanning type display means, and the picture element signals are applied to the scanning type display means thereby to display the pattern thereat comprises means for selectively converting the picture element at a slant portion of the pattern into substantial parallelogram picture element with such slope as to run along the slant line of the slant portion.Type: GrantFiled: March 15, 1979Date of Patent: March 2, 1982Assignee: Nippon Electric Co., Ltd.Inventor: Toshio Oura
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Patent number: 4135125Abstract: A constant voltage circuit comprises an IGFET for deriving an output voltage for a load from a power supply and an inverter circuit responsive to the output voltage for controlling the IGFET in a negative feedback manner to stabilize the output voltage against fluctuations in the supply voltage and the load. The IGFET may be a depletion or an enhancement MOSFET. The inverter circuit preferably comprises an enhancement and a depletion or an enhancement MOSFET. Either a resistor or another IGFET may be connected between the inverter circuit and ground. The constant voltage circuit is readily manufactured as an IC together with an IGFET circuit used as the load.Type: GrantFiled: March 15, 1977Date of Patent: January 16, 1979Assignee: Nippon Electric Co., Ltd.Inventor: Toshio Oura
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Patent number: 4023122Abstract: A signal generating circuit includes a switching circuit that includes two series-connected circuits. Each of the latter includes an enhancement-type MOS FET and a depletion-type MOS FET connected between one terminal of a power source and a junction point of the series-connected circuits. The junction point is used as the output terminal of the switching circuit.Type: GrantFiled: January 23, 1976Date of Patent: May 10, 1977Assignee: Nippon Electric Company, Ltd.Inventor: Toshio Oura