Patents by Inventor Toshio Shimizu
Toshio Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6906258Abstract: An enameled wire capable of improving withstand lifetime with respect to the application of surge voltage of an inverter and thermal degradation thereof while restricting an amount of an inorganic filler material is provided. The enameled wire includes an electrically conductive wire (11) and a coating (12) formed of a high molecular compound uniformly mixed with an inorganic filler material in the form of fine flat particles provided around the electrically conductive wire (11). The enameled wire may include an electrically conductive wire (21), a coating (23) formed of a polyester imide resin solution mixed with an inorganic filler material in the form of fine flat particles and provided on the conductive wire and a coating (24) formed of polyamide imide and provided on the coating (23).Type: GrantFiled: July 16, 2003Date of Patent: June 14, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hisayuki Hirai, Susumu Kojima, Tamon Ozaki, Toshio Shimizu, Takahiro Imai, Hiroki Sekiya, Isao Onodera
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Publication number: 20050113958Abstract: In the processing preparation operation for checking a processing program and the tool compensation amount, a series of confirmation operations for all the tools are easily made using the processing program as conventionally used, without having limitations on the creation of the processing program. When a read skip signal 110 is externally input into a numerical control apparatus, the same instruction as stored in mandatory execution instruction storing means 104 is executed, when commanded in the processing program 100, until the same instruction as stored in read skip end instruction storing means 105 is commanded, but the other instructions are skipped, until the same instruction as stored in read skip end instruction storing means 105 is commanded. Then, when the instruction stored in the read skip end instruction storing means 105 is read, the instruction and subsequent instructions are executed.Type: ApplicationFiled: February 20, 2003Publication date: May 26, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Toshio Shimizu, Takahisa Tanaka, Takeo Teshima
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Patent number: 6897396Abstract: By molding a plurality of vacuum valves (7), (13) having differing functions together with an input member (3) and an output member (21) en bloc in a resin layer (23) to form a switch gear (1), the present invention seeks to achieve dielectric strength without resorting to the use of SF6 gas, while rendering the whole device more compact and reducing both the number of parts and the man hours required for molding.Type: GrantFiled: December 1, 2000Date of Patent: May 24, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yoshihiro Ito, Susumu Kinoshita, Satoshi Makishima, Hiroki Sekiya, Masaru Miyagawa, Toshio Shimizu
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Patent number: 6894670Abstract: A liquid crystal display apparatus for displaying an image on a liquid crystal cell through a liquid crystal driver driven by a predetermined number of bits by inputting image data in which one pixel is represented with a plurality of sub-pixels. The liquid crystal display apparatus includes: memory for storing information about an offset for converting gray level coordinates of a gamma characteristic spaced evenly according to the number of bits into gray level coordinates spaced unevenly; a gray level adjustment portion for performing a calculation on particular input sub-pixel data based on information about the offset stored in the memory; and a pseudo-gray-level-expansion portion for applying pseudo gray level expansion to the sub-pixel data calculated by the gray level adjustment portion. The sub-pixel data to which the pseudo gray level expansion is applied by the pseudo-gray-level-expansion portion is supplied to the liquid crystal driver to display the image on the liquid crystal cell.Type: GrantFiled: April 24, 2001Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: Akihiro Funakoshi, Toshio Shimizu
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Patent number: 6862012Abstract: A white point adjusting apparatus is provided to adjust an achromatic color level for an input video signal including a plurality of color signals, and display an adjusted image on a liquid crystal module. This adjusting apparatus comprises: a first table for setting a white point by deciding an offset quantity of at least one color signal from a highest gray level for each color temperature; a second table for setting an offset quantity of the color signal to converge a halftone white point for each color temperature set by the first table; and a white point adjusting unit for adding the offset quantities set by the first and second tables and to the input video signal.Type: GrantFiled: October 18, 2000Date of Patent: March 1, 2005Assignee: International Business Machines CorporationInventors: Akihiro Funakoshi, Toshio Shimizu, Takuya Ishikawa
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Patent number: 6812136Abstract: According to the present invention, when a wiring layer using copper is formed, an interlayer insulation film is formed on a semiconductor substrate having a conductive portion of an element. A contact hole, which is connected to at least the conductive portion, is formed in the interlayer insulation film. A wiring groove is formed in the surface of the interlayer insulation film including a region where the contact hole is formed. A barrier metal having a tungsten carbide film on its surface is formed on the surface of the interlayer insulation film and in the wiring groove and contact hole in contact with the conductive portion. A copper film is then formed on the barrier metal in contact with the tungsten carbide film. After that, the contact hole and wiring groove are completely filled with the copper film by heat treatment. An excess portion is removed from the copper film except in the contact hole and wiring groove thereby to form a copper buried wiring layer.Type: GrantFiled: March 7, 2001Date of Patent: November 2, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Mitsutoshi Koyama, Toshio Shimizu, Takeshi Kubota
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Publication number: 20040200636Abstract: An enameled wire capable of improving withstand lifetime with respect to the application of surge voltage of an inverter and thermal degradation thereof while restricting an amount of an inorganic filler material is provided. The enameled wire comprises an electrically conductive wire (11) and a coating (12) formed of a high molecular compound uniformly mixed with an inorganic filler material in the form of fine flat particles provided around the electrically conductive wire (11). The enameled wire may comprise an electrically conductive wire (21), a coating (23) formed of a polyester imide resin solution mixed with an inorganic filler material in the form of fine flat particles and provided on the conductive wire and a coating (24) formed of polyamide imide and provided on the coating (23).Type: ApplicationFiled: July 16, 2003Publication date: October 14, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Hisayuki Hirai, Susumu Kojima, Tamon Ozaki, Toshio Shimizu, Takahiro Imai, Hiroki Sekiya, Isao Onodera
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Publication number: 20030168729Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.Type: ApplicationFiled: January 27, 2003Publication date: September 11, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yutaka Ishiwata, Kosoku Nagata, Toshio Shimizu, Hiroyuki Hiramoto, Yasuhiko Taniguchi, Kouji Araki, Hiroshi Fukuyoshi, Hiroshi Komorita
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Patent number: 6605868Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.Type: GrantFiled: December 9, 1999Date of Patent: August 12, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Yutaka Ishiwata, Kosoku Nagata, Toshio Shimizu, Hiroyuki Hiramoto, Yasuhiko Taniguchi, Kouji Araki, Hiroshi Fukuyoshi, Hiroshi Komorita
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Patent number: 6597063Abstract: A package for a semiconductor power device which comprises: a conductive bottom plate as a heat sink; an insulating substrate mounted on the bottom plate; a copper film formed on the insulating substrate to expose a peripheral region of the insulating substrate; semiconductor chips disposed on the copper film; a container arranged on the bottom plate, surrounding the insulating substrate; an external terminal supported through the container and connected electrically with the semiconductor chips; and a silicone gel filled within the container, wherein a solidified insulating material is disposed on an outer edge region of the copper film and the peripheral region of the insulating substrate. Thus, reducing an electric field across the interface and making it difficult to cause a creeping discharge. A notch is formed in the bottom plate, and the notch is filled with a high heat conductive resin. The notch is located outwardly apart from a region where the semiconductor chips are mounted.Type: GrantFiled: April 4, 2000Date of Patent: July 22, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Toshio Shimizu, Hiroyuki Hiramoto, Hiroki Sekiya, Kenji Kigima
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Patent number: 6543667Abstract: A cartridge body 602 is formed with a receptacle chamber 603 for accommodating sheet staples ST therein in a stacked state and is also formed with a drive-out passage 601 for driving out the sheet staples ST, and within the cartridge body 602 is provided a plate spring 520 for pressing the sheet staples ST stacked in the receptacle chamber 603 toward the drive-out passage 601.Type: GrantFiled: December 29, 2000Date of Patent: April 8, 2003Assignee: MAX Co., Ltd.Inventors: Toru Yoshie, Toshio Shimizu
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Publication number: 20020066953Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.Type: ApplicationFiled: December 9, 1999Publication date: June 6, 2002Inventors: YUTAKA ISHIWATA, KOSOKU NAGATA, TOSHIO SHIMIZU, HIROYUKI HIRAMOTO, YASUHIKO TANIGUCHI, KOUJI ARAKI, HIROSHI FUKUYOSHI, HIROSHI KOMORITA
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Patent number: 6366262Abstract: A method and apparatus are provided for supporting multiple display sessions through a single address on a non-programmable-terminal (NPT) attached to a host computer by a work station controller (WSC). The WSC enables shared addressing of multiple display sessions on the NPT. The WSC changes focus to a selected one of the multiple display sessions responsive to receiving from the host computer a data stream for a requested display session not having the focus and responsive to receiving a change focus request from the NPT. The NPT may have one display session active for the user interface and a different display session having the focus communicating with the host computer, which is transparent to the user and to the host computer.Type: GrantFiled: March 7, 1997Date of Patent: April 2, 2002Assignee: International Business Machines CorporationInventors: Steven Joseph Amell, Harvey Gene Kiel, Raymond Francis Romon, Shoji Okimoto, Toshio Shimizu
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Publication number: 20010033262Abstract: A liquid crystal display apparatus for displaying an image on a liquid crystal cell through a liquid crystal driver driven by a predetermined number of bits by inputting image data in which one pixel is represented with a plurality of sub-pixels. The liquid crystal display apparatus includes: memory for storing information about an offset for converting gray level coordinates of a gamma characteristic spaced evenly according to the number of bits into gray level coordinates spaced unevenly; a gray level adjustment portion for performing a calculation on particular input sub-pixel data based on information about the offset stored in the memory; and a pseudo-gray-level-expansion portion for applying pseudo gray level expansion to the sub-pixel data calculated by the gray level adjustment portion. The sub-pixel data to which the pseudo gray level expansion is applied by the pseudo-gray-level-expansion portion is supplied to the liquid crystal driver to display the image on the liquid crystal cell.Type: ApplicationFiled: April 24, 2001Publication date: October 25, 2001Applicant: IBMInventors: Akihiro Funakoshi, Toshio Shimizu
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Publication number: 20010010401Abstract: According to the present invention, when a wiring layer using copper is formed, an interlayer insulation film is formed on a semiconductor substrate having a conductive portion of an element. A contact hole, which is connected to at least the conductive portion, is formed in the interlayer insulation film. A wiring groove is formed in the surface of the interlayer insulation film including a region where the contact hole is formed. A barrier metal having a tungsten carbide film on its surface is formed on the surface of the interlayer insulation film and in the wiring groove and contact hole in contact with the conductive portion. A copper film is then formed on the barrier metal in contact with the tungsten carbide film. After that, the contact hole and wiring groove are completely filled with the copper film by heat treatment. An excess portion is removed from the copper film except in the contact hole and wiring groove thereby to form a copper buried wiring layer.Type: ApplicationFiled: March 7, 2001Publication date: August 2, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsutoshi Koyama, Toshio Shimizu, Takeshi Kubota
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Publication number: 20010004988Abstract: A cartridge body 602 is formed with a receptacle chamber 603 for accommodating sheet staples ST therein in a stacked state and is also formed with a drive-out passage 601 for driving out the sheet staples ST, and within the cartridge body 602 is provided a plate spring member 650 as a pushing means for pushing the sheet staples ST stacked in the receptacle chamber 603 toward the drive-out passage 601.Type: ApplicationFiled: December 29, 2000Publication date: June 28, 2001Inventors: Toru Yoshie, Toshio Shimizu
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Publication number: 20010002666Abstract: By molding a plurality of vacuum valves (7), (13) having differing functions together with an input member (3) and an output member (21) en bloc in a resin layer (23) to form a switch gear (1), the present invention seeks to achieve dielectric strength without resorting to the use of SF6 gas, while rendering the whole device more compact and reducing both the number of parts and the man hours required for molding.Type: ApplicationFiled: December 1, 2000Publication date: June 7, 2001Inventors: Yoshihiro Ito, Susumu Kinoshita, Satoshi Makishima, Hiroki Sekiya, Masaru Miyagawa, Toshio Shimizu
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Patent number: 6201696Abstract: A package for a semiconductor power device which comprises: a conductive bottom plate as a heat sink; an insulating substrate mounted on the bottom plate; a copper film formed on the insulating substrate to expose a peripheral region of the insulating substrate; semiconductor chips disposed on the copper film; a container arranged on the bottom plate, surrounding the insulating substrate; an external terminal supported through the container and connected electrically with the semiconductor chips; and a silicone gel filled within the container, wherein a solidified insulating material is disposed on an outer edge region of the copper film and the peripheral region of the insulating substrate. Thus, reducing an electric field across the interface and making it difficult to cause a creeping discharge. A notch is formed in the bottom plate, and the notch is filled with a high heat conductive resin. The notch is located outwardly apart from a region where the semiconductor chips are mounted.Type: GrantFiled: December 8, 1998Date of Patent: March 13, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Toshio Shimizu, Hiroyuki Hiramoto, Hiroki Sekiya, Kenji Kigima
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Patent number: D507165Type: GrantFiled: February 25, 2004Date of Patent: July 12, 2005Assignee: Max Kabushiki Kaisha (Max Co., Ltd).Inventors: Kazuhiko Kishi, Toshio Shimizu, Kazuo Higuchi
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Patent number: D507729Type: GrantFiled: February 25, 2004Date of Patent: July 26, 2005Assignee: Max Co., Ltd.Inventors: Kazuhiko Kishi, Toshio Shimizu, Kazuo Higuchi