Abstract: There is provided a driving circuit of a liquid crystal display device capable of solving a problem of power consumption while solving a problem of time required for charge/discharge of source lines by virtue of shorting by use of precharge. The driving circuit of the liquid crystal display device comprises first shorting means, second shorting means, third shorting means, and fourth shorting means. With the use of the fourth shorting means, in particular, the source lines can be driven starting from a predetermined potential generated by a gradation voltage generation circuit, and a drive start potential is changed from a conventional common electrode potential to potentials generated by the gradation voltage generation circuit, so that power consumption can be effectively reduced (by about 8% on average as compared with the conventional case).

Abstract: An LSI chip includes a plurality of output terminals and a test circuit. The test circuit includes a single test signal input terminal, a single test signal output terminal, a shift register, and a plurality of switches. The shift register includes an input terminal, which is connected to the test signal input terminal, output bits of the shift register being equal to a number of the output terminals of the LSI chip, and a voltage level of one of the output bits of the shift register being different from these of other output bits of the shift register in response to a clock pulse. Each switch includes an input terminal, an output terminal and a control terminal.

Abstract: A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence. One of the selected reference voltages is supplied through a resistor and a switching device, connected in series, to the output terminal of the converter. The other selected reference voltage is supplied through another resistor and another switching device, connected in series, to the same output terminal. This arrangement saves space, and enables variations in the output voltage levels to-be kept within tolerance by use of resistors with sufficiently high resistance values.

Abstract: An LSI chip includes a plurality of output terminals and a test circuit. The test circuit includes a single test signal input terminal, a single test signal output terminal, a shift register, and a plurality of switches. The shift register includes an input terminal, which is connected to the test signal input terminal, output bits of the shift register being equal to a number of the output terminals of the LSI chip, and a voltage level of one of the output bits of the shift register being different from these of other output bits of the shift register in response to a clock pulse. Each switch includes an input terminal, an output terminal and a control terminal.

Abstract: A level shifter circuit includes first and second reference potential supply lines; first and second output potential supply circuits each connected between the first and second reference potential supply lines; first and second input lines; first and second output lines; and a stress test circuit which functions to, during normal operation, when the first input signal and the second input signal are input to the first input line and the second input line, output the first output signal and the second output signal having respectively different potentials for the first output line and the second output line, and during the stress test, when the first input signal and the second input signal are input to the first input line and the second input line, output signals having identical potentials from the first output line and the second output line.

Abstract: A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence. One of the selected reference voltages is supplied through a resistor and a switching device, connected in series, to the output terminal of the converter. The other selected reference voltage is supplied through another resistor and another switching device, connected in series,.to the same output terminal. This arrangement saves space, and enables variations in the output voltage levels to-be kept within tolerance by use of resistors with sufficiently high resistance values.

Abstract: A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence. One of the selected reference voltages is supplied through a resistor and a switching device, connected in series, to the output terminal of the converter. The other selected reference voltage is supplied through another resistor and another switching device, connected in series, to the same output terminal. This arrangement saves space, and enables variations in the output voltage levels to be kept within tolerance by use of resistors with sufficiently high resistance values.

Abstract: There is provided a driving circuit of a liquid crystal display device capable of solving a problem of power consumption while solving a problem of time required for charge/discharge of source lines by virtue of shorting by use of precharge. The driving circuit of the liquid crystal display device comprises first shorting means, second shorting means, third shorting means, and fourth shorting means. With the use of the fourth shorting means, in particular, the source lines can be driven starting from a predetermined potential generated by a gradation voltage generation circuit, and a drive start potential is changed from a conventional common electrode potential to potentials generated by the gradation voltage generation circuit, so that power consumption can be effectively reduced (by about 8% on average as compared with the conventional case).

Abstract: A level shifter circuit includes first and second reference potential supply lines; first and second output potential supply circuits each connected between the first and second reference potential supply lines; first and second input lines; first and second output lines; and a stress test circuit which functions to, during normal operation, when the first input signal and the second input signal are input to the first input line and the second input line, output the first output signal and the second output signal having respectively different potentials for the first output line and the second output line, and during the stress test, when the first input signal and the second input signal are input to the first input line and the second input line, output signals having identical potentials from the first output line and the second output line.

Abstract: A level shifter circuit includes first and second reference potential supply lines; first and second output potential supply circuits each connected between the first and second reference potential supply lines; first and second input lines; first and second output lines; and a stress test circuit which functions to, during normal operation, when the first input signal and the second input signal are input to the first input line and the second input line, output the first output signal and the second output signal having respectively different potentials for the first output line and the second output line, and during the stress test, when the first input signal and the second input signal are input to the first input line and the second input line, output signals having identical potentials from the first output line and the second output line.

Abstract: There is provided a driving circuit of a liquid crystal display device capable of solving a problem of power consumption while solving a problem of time required for charge/discharge of source lines by virtue of shorting by use of precharge. The driving circuit of the liquid crystal display device comprises first shorting means, second shorting means, third shorting means, and fourth shorting means. With the use of the fourth shorting means, in particular, the source lines can be driven starting from a predetermined potential generated by a gradation voltage generation circuit, and a drive start potential is changed from a conventional common electrode potential to potentials generated by the gradation voltage generation circuit, so that power consumption can be effectively reduced (by about 8% on average as compared with the conventional case).

Abstract: A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence, according to digital input. A switching network charges a capacitor according to the difference between the two selected reference voltages, then connects another capacitor to the first capacitor to generate a voltage intermediate between the two selected reference voltages by redistributing charge between the capacitors. The switching network also selects one of the selected reference voltages or the intermediate voltage as the analog output voltage. This conversion scheme saves space with little or no increase in current consumption.

Abstract: A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence. One of the selected reference voltages is supplied through a resistor and a switching device, connected in series, to the output terminal of the converter. The other selected reference voltage is supplied through another resistor and another switching device, connected in series, to the same output terminal This arrangement saves space, and enables variations in the output voltage levels to be kept within tolerance by use of resistors with sufficiently high resistance values.

Abstract: A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence. One of the selected reference voltages is supplied through a resistor and a switching device, connected in series, to the output terminal of the converter. The other selected reference voltage is supplied through another resistor and another switching device, connected in series, to the same output terminal. This arrangement saves space, and enables variations in the output voltage levels to be kept within tolerance by use of resistors with sufficiently high resistance values.

Abstract: A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence. One of the selected reference voltages is supplied through a resistor and a switching device, connected in series, to the output terminal of the converter. The other selected reference voltage is supplied through another resistor and another switching device, connected in series, to the same output terminal. This arrangement saves space, and enables variations in the output voltage levels to be kept within tolerance by use of resistors with sufficiently high resistance values.

Abstract: A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence, according to digital input. A switching network charges a capacitor according to the difference between the two selected reference voltages, then connects another capacitor to the first capacitor to generate a voltage intermediate between the two selected reference voltages by redistributing charge between the capacitors. The switching network also selects one of the selected reference voltages or the intermediate voltage as the analog output voltage. This conversion scheme saves space with little or no increase in current consumption.

Abstract: A level shifter circuit includes first and second reference potential supply lines; first and second output potential supply circuits each connected between the first and second reference potential supply lines; first and second input lines; first and second output lines; and a stress test circuit which functions to, during normal operation, when the first input signal and the second input signal are input to the first input line and the second input line, output the first output signal and the second output signal having respectively different potentials for the first output line and the second output line, and during the stress test, when the first input signal and the second input signal are input to the first input line and the second input line, output signals having identical potentials from the first output line and the second output line.

Abstract: There is provided a driving circuit of a liquid crystal display device capable of solving a problem of power consumption while solving a problem of time required for charge/discharge of source lines by virtue of shorting by use of precharge. The driving circuit of the liquid crystal display device comprises first shorting means, second shorting means, third shorting means, and fourth shorting means. With the use of the fourth shorting means, in particular, the source lines can be driven starting from a predetermined potential generated by a gradation voltage generation circuit, and a drive start potential is changed from a conventional common electrode potential to potentials generated by the gradation voltage generation circuit, so that power consumption can be effectively reduced (by about 8% on average as compared with the conventional case).

Abstract: An LSI chip includes a plurality of output terminals and a test circuit. The test circuit includes a single test signal input terminal, a single test signal output terminal, a shift register, and a plurality of switches. The shift register includes an input terminal, which is connected to the test signal input terminal, output bits of the shift register being equal to a number of the output terminals of the LSI chip, and a voltage level of one of the output bits of the shift register being different from these of other output bits of the shift register in response to a clock pulse. Each switch includes an input terminal, an output terminal and a control terminal.

Abstract: An oscillation stop detection circuit comprises delay means for delaying an oscillation signal having a predetermined cycle by a predetermined time to thereby output a delayed signal therefrom, detecting means for exclusive-ORing the oscillation signal and the delayed signal to thereby detect the presence of the oscillation signal and outputting a pulse signal in the predetermined cycle when the oscillation signal exists, and charge and discharge means having a capacitor electrically connected between an output node for outputting a detection signal indicative of whether the oscillation signal is at a stop and a source potential or a ground potential, and for discharging the capacitor when the pulse signal is supplied and charging the capacitor according to a predetermined time constant while the pulse signal is unsupplied.