Patents by Inventor Toshio Terano
Toshio Terano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8520463Abstract: A memory macro includes: a plurality of memory cells arranged in a matrix; a plurality of word lines corresponding to rows of the plurality of memory cells; and a plurality of word line drivers configured to drive the plurality of word lines. The voltage of the word lines in their activated state is set to vary with threshold voltage characteristics of a p-channel transistor and an n-channel transistor.Type: GrantFiled: February 23, 2012Date of Patent: August 27, 2013Assignee: Panasonic CorporationInventors: Norihiko Sumitani, Toshio Terano
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Patent number: 8345470Abstract: A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.Type: GrantFiled: January 11, 2011Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Katsuji Satomi, Toshio Terano, Kazuhiro Takemura, Marefusa Kurumada
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Publication number: 20120155211Abstract: A memory macro includes: a plurality of memory cells arranged in a matrix; a plurality of word lines corresponding to rows of the plurality of memory cells; and a plurality of word line drivers configured to drive the plurality of word lines. The voltage of the word lines in their activated state is set to vary with threshold voltage characteristics of a p-channel transistor and an n-channel transistor.Type: ApplicationFiled: February 23, 2012Publication date: June 21, 2012Applicant: Panasonic CorporationInventors: NORIHIKO SUMITANI, TOSHIO TERANO
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Patent number: 8077530Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.Type: GrantFiled: April 11, 2011Date of Patent: December 13, 2011Assignee: Panasonic CorporationInventors: Satoshi Ishikura, Marefusa Kurumada, Hiroaki Okuyama, Yoshinobu Yamagami, Toshio Terano
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Publication number: 20110188327Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.Type: ApplicationFiled: April 11, 2011Publication date: August 4, 2011Applicant: PANASONIC CORPORATIONInventors: Satoshi ISHIKURA, Marefusa Kurumada, Hiroaki Okuyama, Yoshinobu Yamagami, Toshio Terano
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Patent number: 7948787Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.Type: GrantFiled: September 9, 2010Date of Patent: May 24, 2011Assignee: Panasonic CorporationInventors: Satoshi Ishikura, Marefusa Kurumada, Hiroaki Okuyama, Yoshinobu Yamagami, Toshio Terano
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Publication number: 20110103126Abstract: A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.Type: ApplicationFiled: January 11, 2011Publication date: May 5, 2011Applicant: PANASONIC CORPORATIONInventors: Katsuji SATOMI, Toshio Terano, Kazuhiro Takemura, Marefusa Kurumada
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Patent number: 7872893Abstract: A semiconductor memory device having a hierarchical bit line structure includes memory cells and an amplification circuit for amplifying a signal read from one of the memory cells via a bit line. A cell N-well region in which the P-channel transistors of the memory cell are formed and an amplification-circuit N-well region in which the P-channel transistors of the amplification circuit are formed are formed continuously.Type: GrantFiled: December 20, 2007Date of Patent: January 18, 2011Assignee: Panasonic CorporationInventors: Marefusa Kurumada, Satoshi Ishikura, Toshio Terano
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Publication number: 20110007575Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.Type: ApplicationFiled: September 9, 2010Publication date: January 13, 2011Applicant: Panasonic CorporationInventors: Satoshi ISHIKURA, Marefusa KURUMADA, Hiroaki OKUYAMA, Yoshinobu YAMAGAMI, Toshio TERANO
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Patent number: 7839697Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.Type: GrantFiled: December 20, 2007Date of Patent: November 23, 2010Assignee: Panasonic CorporationInventors: Satoshi Ishikura, Marefusa Kurumada, Hiroaki Okuyama, Yoshinobu Yamagami, Toshio Terano
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Patent number: 7692955Abstract: A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.Type: GrantFiled: February 28, 2008Date of Patent: April 6, 2010Assignee: Panasonic CorporationInventors: Yutaka Terada, Satoshi Ishikura, Yoshinobu Yamagami, Toshio Terano
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Patent number: 7453118Abstract: To propose a new channel structure suitable for high efficiency source side injection, and provide a non-volatile semiconductor memory device and a charge injection method using the same. The non-volatile memory device includes a first conductivity type semiconductor substrate (SUB), a first conductivity type inversion layer-forming region (CH1), second conductivity type accumulation layer-forming regions (ACLa, ACL2b), second conductivity type regions (S/D1, S/D2), an insulating film (GD0) and a first conductive layer (CL) formed on the inversion layer-forming region (CH1). A charge accumulation film (GD) and a second conductive layer (WL) are stacked on an upper surface and side surface of the first conductive layer (CL), an exposure surface of the inversion layer-forming region (CH1), and an upper surface of the accumulation layer-forming regions (ACLa, ACLb) and the second conductivity type regions (S/D1, S/D2).Type: GrantFiled: March 9, 2005Date of Patent: November 18, 2008Assignee: Sony CorporationInventors: Hideto Tomiie, Toshio Terano, Toshio Kobayashi
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Publication number: 20080253171Abstract: A semiconductor integrated circuit includes: a memory cell array including a plurality of SRAM memory cells; a characteristic measuring circuit including a plurality of transistor circuits connected in parallel; and a first terminal. The plurality of transistor circuits each include a first transistor configured in the same manner as one of transistors included in one of the SRAM memory cells. The first transistor is connected so as to control current between the first terminal and a node at a reference potential according to a voltage supplied to a gate of the first transistor.Type: ApplicationFiled: February 28, 2008Publication date: October 16, 2008Inventors: Yutaka Terada, Satoshi Ishikura, Yoshinobu Yamagami, Toshio Terano
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Publication number: 20080151606Abstract: A semiconductor memory device having a hierarchical bit line structure includes memory cells and an amplification circuit for amplifying a signal read from one of the memory cells via a bit line. A cell N-well region in which the P-channel transistors of the memory cell are formed and an amplification-circuit N-well region in which the P-channel transistors of the amplification circuit are formed are formed continuously.Type: ApplicationFiled: December 20, 2007Publication date: June 26, 2008Inventors: Marefusa KURUMADA, Satoshi Ishikura, Toshio Terano
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Publication number: 20080151653Abstract: A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit.Type: ApplicationFiled: December 20, 2007Publication date: June 26, 2008Inventors: Satoshi ISHIKURA, Marefusa Kurumada, Hiroaki Okuyama, Yoshinobu Yamagami, Toshio Terano
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Patent number: 7227255Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.Type: GrantFiled: April 5, 2005Date of Patent: June 5, 2007Assignee: Sony CorporationInventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
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Patent number: 7049180Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.Type: GrantFiled: April 5, 2005Date of Patent: May 23, 2006Assignee: Sony CorporationInventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
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Patent number: 7023061Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.Type: GrantFiled: March 7, 2005Date of Patent: April 4, 2006Inventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
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Patent number: 7012329Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.Type: GrantFiled: April 5, 2005Date of Patent: March 14, 2006Assignee: Sony CorporationInventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano
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Publication number: 20050255652Abstract: A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.Type: ApplicationFiled: April 5, 2005Publication date: November 17, 2005Inventors: Kazumasa Nomoto, Toshio Kobayashi, Akihiro Nakamura, Ichiro Fujiwara, Toshio Terano