Abstract: A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

Abstract: A multi-gray level display designed to display multi-gray level images free of flicker or the like, by using a small number of voltages. The display comprises a first gray-level pattern generating circuit 311 for generating a first gray-level pattern which acquires a gray level during m frame periods, a second gray-level pattern generating circuit 321 for generating a second gray-level pattern which acquires another gray level during n frame periods (n is a positive integer greater than m), and a selection circuit 341 for selecting and outputting one of the preset voltages, in accordance with an output from the first gray-level pattern generating circuit 311 or the second gray-level pattern generating circuit 321 when the input multi-gray level display data corresponds to a gray level of either the first gray-level pattern or the second gray-level pattern.

Abstract: A matrix-addressed liquid crystal display device is constructed of a pair of substrates facing each other with liquid crystal cells arranged in n rows and m columns on one of the substrates. Switches included in each cell comprise field effect transistors with n address lines forming a common connection for the gate electrodes of the field effect transistors in each row and m signal lines forming a common connection for the drain electrode or source electrode of the field effect transistors in each column. A common electrode is arranged on the other substrate and a liquid crystal layer interposed between the substrates. An address line drive circuit supplies a sequential scanning signal to the n address lines; and, a signal line drive circuit supplies a display signal to the m signal lines.An asymmetrical display signal is selected whereby the voltage applied cross the liquid crystal layer is controlled to be a pure AC signal with no DC component.

Abstract: In an active matrix type display apparatus which includes a first electrode substrate having a transparent insulation substrate on which a thin film transistor a transparent display pixel electrode selectively driven by the thin file transistor and a connecting portion for connecting the thin film transistor with the transparent display pixel electrode are formed, a second electrode substrate having another transparent insulation substrate on which an opposing electrode formed of a transparent conductive film is formed, and a display medium sandwiched between the first and second electrode substrates, an electrically conductive light shielding layer which is fixed at a predetermined potential is provided on each of thin film transistor portions of the first electrode substrate, and a part of the light shielding layer opposes a part of the transparent display pixel electrode through an insulation film so as to form a supplemental storage capacitor.