Patents by Inventor Toshiro FUJISAKI

Toshiro FUJISAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11194380
    Abstract: It is an object of the present invention to provide a technique capable of reducing power consumption of a semiconductor device even when the semiconductor device operates at high speed. The semiconductor device includes a module for outputting a signal, a delay element, a first output circuit having an input and an output, a first external terminal connected to the output of the first output circuit and to be connected to a signal wiring, and a second external terminal. The input of the first output circuit receives the signal delayed by the delay element. The second external terminal receives the signal without passing through the delay element. The signal of the second external terminal is used to change the potential level of the signal wiring to be connected to the first external terminal before the first output circuit changes the potential of the first external terminal based on the delayed signal.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: December 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naotaka Kawakami, Toshiro Fujisaki
  • Patent number: 10802730
    Abstract: Power consumption of a semiconductor device is reduced. A semiconductor device according to an embodiment includes a plurality of circuits, a bus circuit including a plurality of buffers that temporarily store communication data between the circuits and a plurality of arbitration circuits that arbitrate an access between the circuits and the buffers, a storage unit that stores information based on a use state of the buffers during communication between the circuits and configuration information including designation of unused circuits that are not used for the communication from among the circuits, and a control circuit that controls the bus circuit so as to stop use of unused buffers that are not used for the communication from among the buffers and at least a partial configuration in arbitration circuits corresponding to the unused circuits from among the arbitration circuits based on the configuration information.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: October 13, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasumasa Watanabe, Mitsuhiro Ono, Toshiro Fujisaki, Kenji Kimura
  • Publication number: 20200004315
    Abstract: It is an object of the present invention to provide a technique capable of reducing power consumption of a semiconductor device even when the semiconductor device operates at high speed. The semiconductor device includes a module for outputting a signal, a delay element, a first output circuit having an input and an output, a first external terminal connected to the output of the first output circuit and to be connected to a signal wiring, and a second external terminal. The input of the first output circuit receives the signal delayed by the delay element. The second external terminal receives the signal without passing through the delay element. The signal of the second external terminal is used to change the potential level of the signal wiring to be connected to the first external terminal before the first output circuit changes the potential of the first external terminal based on the delayed signal.
    Type: Application
    Filed: June 19, 2019
    Publication date: January 2, 2020
    Inventors: Naotaka KAWAKAMI, Toshiro FUJISAKI
  • Publication number: 20190171377
    Abstract: Power consumption of a semiconductor device is reduced. A semiconductor device according to an embodiment includes a plurality of circuits, a bus circuit including a plurality of buffers that temporarily store communication data between the circuits and a plurality of arbitration circuits that arbitrate an access between the circuits and the buffers, a storage unit that stores information based on a use state of the buffers during communication between the circuits and configuration information including designation of unused circuits that are not used for the communication from among the circuits, and a control circuit that controls the bus circuit so as to stop use of unused buffers that are not used for the communication from among the buffers and at least a partial configuration in arbitration circuits corresponding to the unused circuits from among the arbitration circuits based on the configuration information.
    Type: Application
    Filed: October 4, 2018
    Publication date: June 6, 2019
    Inventors: Yasumasa WATANABE, Mitsuhiro ONO, Toshiro FUJISAKI, Kenji KIMURA
  • Patent number: 10288493
    Abstract: In order to provide a semiconductor integrated circuit capable of predicting its own lifetime (wear out failure) due to the aged deterioration and notifying a warning, it includes a processor, a temperature sensor, a non-volatile memory, and a comparator formed on the same semiconductor substrate. The comparator compares a temperature measured by the temperature sensor with a predetermined temperature threshold, and the non-volatile memory accumulatively holds the information (cumulative time) about a period having the temperature exceeding the temperature threshold. The semiconductor integrated circuit notifies the outward of a warning when the cumulative time having the temperature exceeding the temperature threshold exceeds a predetermined high temperature time threshold.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: May 14, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiro Fujisaki, Takatoshi Tamaoki, Akira Murayama
  • Publication number: 20170059416
    Abstract: In order to provide a semiconductor integrated circuit capable of predicting its own lifetime (wear out failure) due to the aged deterioration and notifying a warning, it includes a processor, a temperature sensor, a non-volatile memory, and a comparator formed on the same semiconductor substrate. The comparator compares a temperature measured by the temperature sensor with a predetermined temperature threshold, and the non-volatile memory accumulatively holds the information (cumulative time) about a period having the temperature exceeding the temperature threshold. The semiconductor integrated circuit notifies the outward of a warning when the cumulative time having the temperature exceeding the temperature threshold exceeds a predetermined high temperature time threshold.
    Type: Application
    Filed: June 30, 2016
    Publication date: March 2, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Toshiro FUJISAKI, Takatoshi TAMAOKI, Akira MURAYAMA