Patents by Inventor Toshiro Hiraoka

Toshiro Hiraoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6649516
    Abstract: Disclosed is a method for manufacturing a composite member comprising a porous substrate, a via, and a wiring. The method comprises exposing a first region and a second region in the porous substrate to a exposure beam through a mask, the second region exposed by the exposure beam not more than 50% of the exposure of the first region, the exposure beam having the wavelength that an average size of voids of the porous substrate is, as expressed by a radius of gyration, {fraction (1/20)} to 10 times, and forming the via and the wiring by infiltrating a conductive material into the first region and the second region respectively.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: November 18, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Yasuyuki Hotta, Shigeru Matake, Toshiro Hiraoka
  • Patent number: 6626724
    Abstract: A display device has an array formed on a substrate including a cathode wiring line layer, a gate wiring line layer and an insulating layer for electrically insulating the cathode wiring line layer and the gate wiring line layer from each other. Holes are formed at the crossing portion between the cathode wiring line layer and the gate wiring line layer so as to penetrate through the insulating layer, and resistive layer and an emitter layer are provided in the holes. The resistive layer has such a structure that conductive fine particles are dispersed in a base material of insulating fine particles, and the emitter layer is formed of a fine particle material. The insulating layer between the cathode electrode lines and the gate electrodes is formed of a silicon oxide film containing fluorine.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: September 30, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Yamamoto, Miki Mori, Yumi Fukuda, Hitoshi Kobayashi, Yujiro Hara, Goh Itoh, Masayuki Saito, Toshiro Hiraoka, Koji Asakawa
  • Publication number: 20030107465
    Abstract: The present invention provides a composite material such as a passive element, a passive element composite component, a substrate with a built-in passive element and a composite wiring substrate which are free from, for example, a layer peeling problem and enables high density packaging with ease. In the present invention, a porous base material is divided into plural functional regions and a material having different electromagnetic characteristics is filled in a pore of the porous base material of each functional region, to form a passive element or a wiring substrate. Among the aforementioned plural functional regions, at least one functional region is a conductive material region filled with a conductive material and other regions are filled with a high-dielectric material, a high-permeability material or a low-dielectric material.
    Type: Application
    Filed: September 23, 2002
    Publication date: June 12, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiro Hiraoka, Yasuyuki Hotta, Koji Asakawa, Shigeru Matake
  • Patent number: 6565764
    Abstract: Molded products may be made by a process comprising preparing a structure comprising a block copolymer or a graft copolymer having two or more phases, wherein each phase is comprised of polymer chains, decomposing the polymer chains of at least one phase of the structure, and cleaning the structure with a supercritical fluid or a sub-critical fluid, thereby removing the decomposed polymer chains from the structure. Molded products made by this method have very low levels of residual solvents, can be manufactured at a relatively low temperature in a short period of time without using large amounts of organic solvents, and without discharging large amounts of liquid waste.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: May 20, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Koji Asakawa, Yasuyuki Hotta
  • Patent number: 6565763
    Abstract: A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc−No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.
    Type: Grant
    Filed: June 7, 2000
    Date of Patent: May 20, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Toshiro Hiraoka, Yoshihiro Akasaka, Yasuyuki Hotta
  • Patent number: 6563260
    Abstract: A display device has an array formed on a substrate including a cathode wiring line layer, a gate wiring line layer and an insulating layer for electrically insulating the cathode wiring line layer and the gate wiring line layer from each other. Holes are formed at the crossing portion between the cathode wiring line layer and the gate wiring line layer so as to penetrate through the insulating layer, and resistive layer and an emitter layer are provided in the holes. The resistive layer has such a structure that conductive fine particles are dispersed in a base material of insulating fine particles, and the emitter layer is formed of a fine particle material. The insulating layer between the cathode electrode lines and the gate electrodes is formed of a silicon oxide film containing fluorine.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: May 13, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Yamamoto, Miki Mori, Yumi Fukuda, Hitoshi Kobayashi, Yujiro Hara, Goh Itoh, Masayuki Saito, Toshiro Hiraoka, Koji Asakawa
  • Publication number: 20030022102
    Abstract: Disclosed is a method of manufacturing a composite member having a conductive pattern, comprising (1) forming on a surface of an insulating body a photosensitive layer containing both a photosensitive compound forming an ion-exchange group upon irradiation with an energy beam and a crosslinkable compound having a crosslinkable group, (2) forming a pattern of ion-exchange groups by selectively exposing the photosensitive layer to an energy beam so as to form an ion-exchange group in the exposed portion, (3) crosslinking the crosslinkable compound contained in at least the exposed portion of the photosensitive layer, (4) allowing metal ions, or a metal colloid to be adsorbed on the pattern of ion-exchange groups formed by the selectively exposing, and (5) forming a composite member having conductive pattern by depositing a conductive material on the pattern of ion-exchange groups having the metal ions, or the metal colloid adsorbed thereon using an electroless plating.
    Type: Application
    Filed: March 7, 2002
    Publication date: January 30, 2003
    Inventors: Toshiro Hiraoka, Koji Asakawa, Yasuyuki Hotta, Shigeru Matake
  • Publication number: 20030001490
    Abstract: A display device has an array formed on a substrate including a cathode wiring line layer, a gate wiring line layer and an insulating layer for electrically insulating the cathode wiring line layer and the gate wiring line layer from each other. Holes are formed at the crossing portion between the cathode wiring line layer and the gate wiring line layer so as to penetrate through the insulating layer, and resistive layer and an emitter layer are provided in the holes. The resistive layer has such a structure that conductive fine particles are dispersed in a base material of insulating fine particles, and the emitter layer is formed of a fine particle material. The insulating layer between the cathode electrode lines and the gate electrodes is formed of a silicon oxide film containing fluorine.
    Type: Application
    Filed: September 5, 2002
    Publication date: January 2, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Yamamoto, Miki Mori, Yumi Fukuda, Hitoshi Kobayashi, Yujiro Hara, Goh Itoh, Masayuki Saito, Toshiro Hiraoka, Koji Asakawa
  • Publication number: 20020197834
    Abstract: Disclosed is a method for manufacturing a composite member comprising a porous substrate, a via, and a wiring. The method comprises exposing a first region and a second region in the porous substrate to a exposure beam through a mask, the second region exposed by the exposure beam not more than 50% of the exposure of the first region, the exposure beam having the wavelength that an average size of voids of the porous substrate is, as expressed by a radius of gyration, {fraction (1/20)} to 10 times, and forming the via and the wiring by infiltrating a conductive material into the first region and the second region respectively.
    Type: Application
    Filed: June 5, 2002
    Publication date: December 26, 2002
    Inventors: Koji Asakawa, Yasuyuki Hotta, Shigeru Matake, Toshiro Hiraoka
  • Patent number: 6465742
    Abstract: Disclosed is a three dimensional structure comprising a porous body and a plurality of regions having a substance loaded in the porous body. An average period of a part of the plural regions loaded with the substance is 0.1 to 2 &mgr;m to form a photonic band.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: October 15, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Koji Asakawa, Yasuyuki Hotta
  • Publication number: 20020136927
    Abstract: A recording medium includes a substrate, and a recording layer formed on the substrate having (a) a recording track band, and (b) recording cells regularly arrayed in the recording track band to form a plurality rows of sub-tracks. The recording cells included in each sub-track are formed apart from each other at a pitch P in the track direction. Nearest neighboring two recording cells, each positioned on adjacent two sub-tracks in the track band, are formed apart from each other at a pitch P/n in the track direction, where 2≦n≦5.
    Type: Application
    Filed: March 22, 2002
    Publication date: September 26, 2002
    Inventors: Hiroyuki Hieda, Masatoshi Sakurai, Koji Asakawa, Toshiro Hiraoka, Katsuyuki Naito
  • Patent number: 6456416
    Abstract: There is provided a process for producing an optical element comprising a photonic crystal in which spots having different indices are arranged periodically, comprising the step of exposing an optical medium whose refractive index changes by irradiation of light or by a predetermined treatment conducted after the irradiation of light according to the intensity of the applied light to a field where light intensity changes in space at a period of the wavelength order of light and holding the optical medium for a given time, and the step of repeating at least once the step of creating another field where light intensity changes in space at a period of the wavelength order of light by shifting the optical medium. Further, by using a plurality of optical media whose refractive indices change by an external field, the refractive indices of certain two media out of these optical media are caused to be the same or about the same under a certain external field condition.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: September 24, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kouichi Ichimura, Toshiro Hiraoka
  • Patent number: 6391471
    Abstract: The present invention provides a multi-component multi-phase type polymeric shaped material in which a plurality of hole- or electron-conducting phases constitute a three-dimensional bicontinuous nano phase separation structure, and a functional device using the same. Such a functional device is quick in response and good in durability. The present invention also relates to a functional device comprising a laminated structure composed of a plurality of layers laminated, and at least one pair of electrodes that penetrate the interface between two layers laminated.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: May 21, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Koji Asakawa
  • Publication number: 20020020946
    Abstract: Molded products may be made by a process comprising preparing a structure comprising a block copolymer or a graft copolymer having two or more phases, wherein each phase is comprised of polymer chains, decomposing the polymer chains of at least one phase of the structure, and cleaning the structure with a supercritical fluid or a sub-critical fluid, thereby removing the decomposed polymer chains from the structure. Molded products made by this method have very low levels of residual solvents, can be manufactured at a relatively low temperature in a short period of time without using large amounts of organic solvents, and without discharging large amounts of liquid waste.
    Type: Application
    Filed: August 13, 2001
    Publication date: February 21, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiro Hiraoka, Koji Asakawa, Yasuyuki Hotta
  • Publication number: 20020004180
    Abstract: Disclosed is a method of manufacturing a composite member in which a conductive portion is selectively formed in an insulator. The method comprises the steps of forming a photosensitive composition layer containing a compound forming an ion-exchange group upon irradiation with light having a wavelength not shorter than 280 nm within or on the surface of an insulator, exposing selectively the photosensitive composition layer to light having a wavelength not shorter than 280 nm, forming an ion-exchange group in the exposed portion, and bonding a metal or metal ions to the ion-exchange group formed in the exposed portion of the photosensitive composition layer.
    Type: Application
    Filed: March 15, 2001
    Publication date: January 10, 2002
    Inventors: Yasuyuki Hotta, Toshiro Hiraoka, Koji Asakawa, Shigeru Matake
  • Patent number: 6025117
    Abstract: A polysilane having a repeating unit represented by the following general formula (LPS-I), ##STR1## wherein A is a bivalent organic group, R.sup.1 substituents may be the same or different and are selected from hydrogen atom and substituted or unsubstituted hydrocarbon group and silyl group. The polysilane is excellent in solublity in an organic solvent so that it can be formed into a film by way of a coating method, which is excellent in mechanical strength and heat resistance. The polysilane can be employed as an etching mask to be disposed under a resist in a manufacturing method of a semiconductor device. The polysilane exhibits anti-reflective effect during exposure, a large etch rate ratio in relative to a resist, and excellent dry etching resistance.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: February 15, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiko Nakano, Rikako Kani, Shuji Hayase, Yasuhiko Sato, Seiro Miyoshi, Toru Ushirogouchi, Sawako Yoshikawa, Hideto Matsuyama, Yasunobu Onishi, Masaki Narita, Toshiro Hiraoka
  • Patent number: 6002522
    Abstract: An optical functional element including two diffraction gratings having metal films formed on their surfaces, which are arranged to oppose each other to form a photonic band, and an optical functional film interposed between these diffraction gratings, the optical functional film consisting of a polymer containing an optical functional material, such as a nonlinear optical material and electro-optic material, dispersed in the polymer.
    Type: Grant
    Filed: June 10, 1997
    Date of Patent: December 14, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Todori, Toshiro Hiraoka, Shuji Hayase
  • Patent number: 5907382
    Abstract: A transparent conductive substrate, that has excellent heat resistant characteristic, shock resisting characteristic, chemical resisting characteristic, oxygen barrier characteristic, steam barrier characteristic, and scratch resisting characteristic while the substrate is easy to handle and has a thin, and light-weight structure, is provided. A display apparatus having such a transparent conductive substrate is also provided.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: May 25, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sadao Kajiura, Toshiro Hiraoka, Akira Yoshizumi
  • Patent number: 5866471
    Abstract: A silicon thin film is formed by coating on a substrate a solution of polysilane represented by the general formula --(SiR.sup.1.sub.2).sub.n --, where R.sup.1 substituents are selected from the group consisting of hydrogen, an alkyl group having two or more carbon atoms and a .beta.-hydrogen, a phenyl group and a silyl group, and thermally decomposing the polysilane to deposit silicon.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: February 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuro Beppu, Shuji Hayase, Atsushi Kamata, Kenji Sano, Toshiro Hiraoka
  • Patent number: 5858541
    Abstract: A glass composite material comprising a polymer chain selected from the group consisting of polysilane, polygermane, polystannane and a copolymer thereof, and a network structure of a metal oxide consisting of a metal atom bonded to the other metal atom through an oxygen atom, wherein the polymer chain is chemically crosslinked with a glass matrix of the network structure of the metal oxide directly or indirectly, and a volume resistivity measured by setting a ratio of a voltage to a film thickness at 10.sup.6 V/cm according to a disc plate electrode method is not more than 3.times.10.sup.6 .OMEGA.cm.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: January 12, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiro Hiraoka, Yutaka Majima, Kenji Todori, Julian R. Koe, Yoshihiko Nakano, Shinji Murai, Shuzi Hayase