Abstract: A wire holder is provided which allows for reduced number of process steps required in bundling wires. The wire holder is for relative alignment of a plurality of wires upon bundling the wires, and includes a plurality of wall portions formed rotationally symmetric to one another, provided to project in a direction orthogonal to an axis O serving as a rotation symmetry axis, and extending along the axis O. Between opposite ones of the wall portions, recesses each having an arc shape in cross section are formed to hold the wires. Each of the recesses has a span length of not less than 85% of the diameter of each of the wires. By fitting the wires into the recesses and arranging them along the rotation symmetry axis, the wires can be aligned.

Abstract: A semiconductor memory device includes a switch that turns on or off connection between a write data line pair which is an output of a write buffer and read data line pair. For a Write Data Through function, the switch is turned on in response to an activated one-shot pulse and a sense amplifier activation signal, thereby approximately equalizing data hold time tOHW in the Write Data Through function and data hold time tOHR in a read operation.

Abstract: Disclosed is a semiconductor memory device which comprises an internal clock generating circuit receiving a clock signal from outside to generate an internal clock signal to be supplied to a random access memory. The internal clock generating circuit includes a circuit for canceling internal clock generation for generating a signal activating an internal clock signal during operation based on an external clock signal, a chip select signal and a write enable signal, and a circuit for setting the internal clock signal based on an output of the circuit for canceling internal clock generation and for resetting the internal clock signal based on an internal clock reset signal. A dummy cycle is provided next to a write cycle.

Abstract: A semiconductor memory device includes a switch that turns on or off connection between a write data line pair which is an output of a write buffer and read data line pair. For a Write Data Through function, the switch is turned on in response to an activated one-shot pulse and a sense amplifier activation signal, thereby approximately equalizing data hold time tOHW in the Write Data Through function and data hold time tOHR in a read operation.

Abstract: Disclosed is a semiconductor memory device which comprises an internal clock generating circuit receiving a clock signal from outside to generate an internal clock signal to be supplied to a random access memory. The internal clock generating circuit includes a circuit for canceling internal clock generation for generating a signal activating an internal clock signal during operation based on an external clock signal, a chip select signal and a write enable signal, and a circuit for setting the internal clock signal based on an output of the circuit for canceling internal clock generation and for resetting the internal clock signal based on an internal clock reset signal. A dummy cycle is provided next to a write cycle.