Abstract: A semiconductor device includes a semiconductor substrate having a main surface, and a laminated structure. The laminated structure is made up of a nonmonocrystalline silicon layer and a layer of refractory metal or refractory metal silicide, formed on the nonmonocrystalline silicon layer, and formed on the main surface of the semiconductor substrate. The resistivity of the nonmonocrystalline silicon layer is set at less than substantially 1.times.10.sup.-2 .OMEGA..multidot.cm by doping an impurity thereinto at the time of deposition of the nonmonocrystalline silicon layer.

Abstract: A semiconductor device with an electrode wiring structure comprises at least one diffused region provided in a semiconductor substrate, a silicon oxide layer covering the substrate surface, a silicon nitride layer provided on the silicon oxide layer, a through-hole reaching the diffused region through the silicon oxide layer from an upper surface of the silicon nitride layer, a silicon semiconductor layer filled in the through-hole and serving as an electrode wiring layer, and an interconnection layer electrically connected to the diffused region through the silicon semiconductor layer. According to the structure, since the silicon oxide layer is covered with the silicon nitride layer, unwanted contaminations such as phosphorus, boron, etc., previously contained in the silicon oxide layer are not added to the silicon semiconductor layer during its growth process. Therefore, the electrode wiring layer of silicon semiconductor having controlled conductivity can be provided.

Abstract: A semiconductor device with an electrode wiring structure comprises at least one diffused region provided in a semiconductor substrate, a silicon oxide layer covering the substrate surface, a silicon nitride layer provided on the silicon oxide layer, a through-hole reaching the diffused region through the silicon oxide layer from an upper surface of the silicon nitride layer, a silicon semiconductor layer filled in the through-hole and serving as an electrode wiring layer, and an interconnection layer electrically connected to the diffused region through the silicon semiconductor layer. According to the structure, since the silicon oxide layer is covered with the silicon nitride layer, unwanted contaminations such as phosphorus, boron, etc., previously contained in the silicon oxide layer are not added to the silicon semiconductor layer during its growth process. Therefore, the electrode wiring layer of silicon semiconductor having controlled conductivity can be provided.

Abstract: In the selective anisotropic etching by RIE of a first poly-Si film formed on a gate oxide film the poly-Si film is not entirely removed such that the poly-Si film is partly left unremoved. Then, the entire surface is covered with a second poly-Si film, followed by applying RIE. This particular technique permits preventing the gate oxide film near a poly-Si gate and the interface between the gate oxide film and the substrate from being damaged. Finally, a chemical dry etching, which does not do damage to the gate insulation film near the poly-Si gate, is applied to remove the second poly-Si film and the portion of the first polysilicon film thereunder.

Abstract: The solid-state imaging device is applicable to a high sensitivity color camera although its structure is as simple as that of a monochromatic camera, and comprises a semiconductor chip in which a large number of pixels are arranged in a matrix form on one surface of a semiconductor substrate, and an optical grating body for separating an incident light into rays of light to allow them to be incident to the pixel trains in one direction on the chip. The optical grating body includes optical gratings arranged at a pitch corresponding to two or three pixels of a pixel train in a direction perpendicular to the above-mentioned one direction, having a fixed inclination relative to the substrate surface, and juxtaposed provided in the above-mentioned one direction, and a supporting surface for supporting the gratings so that they have the above-mentioned fixed inclination.

Abstract: An MOS FET of the semiconductor device includes a semiconductor substrate on which a projection is formed via a given film. The projection is made of a polysilicon having grain boundaries. A pair of gate electrodes are provided so that one of the gate electrodes faces the other thereof via side walls of the projection and gate oxide films. A conductive channel forming area is formed at the side walls of the projection, so that the extending direction of the channel is parallel to the thickness direction of the substrate.

Abstract: In a semiconductor memory device having a floating gate structure, the floating gate electrode is composed of 2 to 10 silicon grains. With the floating gate electrode, the insulation film, formed on the floating gate electrode, can have a high breakdown voltage. In a method of manufacturing a semiconductor memory device having a floating gate structure, an insulation film is formed on the silicon substrate, portions of the insulation film which are on the drain and source forming regions of the silicon substrate are removed, and a silicon layer is formed on the silicon substrate by an epitaxial growth process, constituting a floating gate, composed of 2 to 10 silicon grains. According to the manufacturing method, the insulation film formed on the floating gate electrode can have a high breakdown voltage.

Abstract: In the selective etching by RIE, a poly-Si film formed on the gate oxide film is not entirely removed such that the poly-Si film is partly left unremoved. Then, the entire surface is covered with a poly-Si film, followed by applying RIE. The particular technique permits preventing the gate oxide film near a poly-Si gate and the interface between the gate oxide film and the substrate from being damaged. Finally, a chemical dry etching, which does not do damage to the gate insulation film near the poly-Si gate, is applied to remove the poly-Si film.

Abstract: In a semiconductor memory device having a floating gate structure, the floating gate electrode is composed of 2 to 10 silicon grains. With the floating gate electrode, the insulation film, formed on the floating gate electrode, can have a high breakdown voltage. In a method of manufacturing a semiconductor memory device having a floating gate structure, an insulation film is formed on the silicon substrate, portions of the insulation film which are on the drain and source forming regions of the silicon substrate are removed, and a silicon layer is formed on the silicon substrate by an epitaxial growth process, constituting a floating gate, composed of 2 to 10 silicon grains. According to the manufacturing method, the insulation film formed on the floating gate electrode can have a high breakdown voltage.

Abstract: A defect-recognition processing apparatus converts into a defect image pattern, via a television camera, crystal defects present on the surface of an object under inspection, to process an image signal, by means of an image processing device, which corresponds to the defect image pattern, to measure rectangular images in terms of their length and their ratio between L.sub.Y and L.sub.X (L.sub.Y : a length in a longitudinal direction and L.sub.X : a length in the lateral direction of the wafer) and to detect defects developed on the surface of the aforementioned object.

Abstract: A first insulating film of a light-transmitting material is formed on a channel region between the source and drain regions on a semiconductor substrate. A floating gate electrode is formed on the first insulating film. A second insulating film is formed on the floating gate electrode. A control gate electrode is formed on the second insulating film. An opening is formed to extend through the control gate electrode, the second insulating film, and the floating gate electrode. The opening is filled with a light-transmitting material. Light incident on the memory cell is guided by the material onto the channel region. When light becomes incident on the channel region while predetermined voltages are applied to the control gate electrode and across the source and drain regions, electron-hole pairs corresponding to the amount of light incident on the memory cell are generated in the channel region, and the electrons are trapped in the floating gate electrode.

Abstract: A semiconductor device, which is subjected to a thermal treatment process during manufacture of the device, includes a wafer having semiconductor regions insulated from a semiconductor substrate by insulation layers, with at least one semiconductor element formed in each of the semiconductor regions, and at least one semiconductor element formed in the semiconductor substrate. The main surface of the semiconductor regions are substantially in the same plane as the main surface of the semiconductor substrate. The total area of the main surfaces of the semiconductor regions is 30% or less of the area of the wafer to prevent warping of the wafer resulting from the thermal treatment process.

Abstract: A semiconductor device is manufactured by forming a first insulating film on a surface of a semiconductor substrate of a first conductivity type, and a first nonmonocrystalline silicon film is formed on the first insulating film. A second insulating film is deposited on the first nonmonocrystalline silicon film by CVD, sputtering or molecular beam method. An impurity is then ion-implanted in the first nonmonocrystalline silicon film through the second insulating film. The second insulating film is then removed to expose the surface of the first nonmonocrystalline silicon film doped with the impurity, and a thermal oxide film is formed on the exposed portion of the first nonmonocrystalline silicon film. Subsequently, a second nonmonocrystalline silicon film is formed on the thermal oxide film, and a third insulating film is formed on the second nonmonocrystalline silicon film.

Abstract: An apparatus for producing silicon single crystal from melted silicon by the pull-up process using a seed crystal, wherein at least a portion of a device in contact with the melted silicon includes a layer of silicon nitride precipitated from gaseous phase and comprising 20% or above of .beta. phase, or comprising 80% or above of .alpha. phase whose crystal grains have grain diameters of 5 .mu.m or above at a ratio of 10% or more.