Abstract: A semiconductor integrated circuit includes: a plurality of the functional blocks; a plurality of configuration data memories in which a plurality of configuration data are stored; and a plurality of programmable switches configured to control connection between said plurality of functional blocks based on one of the plurality of configuration data which is stored in a common one of said plurality of configuration data memories.

Abstract: A state transition management device includes a first terminal receiving a first signal based on a current state-number, a memory which stores a state transition rule and from which a plurality of subsequent state-number candidates are read out in accordance with the first signal, a plurality of first nodes revealing the plurality of subsequent state-number candidates, a second terminal receiving a second signal based on the current state-number, a selection method specifying unit which outputs a selection method specifying signal in accordance with the second signal, a second node revealing the selection method specifying signal, a event terminal receiving a event-signal based on an event, a third terminal receiving a third signal based on the current state-number, a selection circuit which selects a subsequent state-number from the plurality of subsequent number candidates in accordance with the event-signal and the third signal.

Abstract: A semiconductor integrated circuit includes: a plurality of the functional blocks; a plurality of configuration data memories in which a plurality of configuration data are stored; and a plurality of programmable switches configured to control connection between said plurality of functional blocks based on one of the plurality of configuration data which is stored in a common one of said plurality of configuration data memories.

Abstract: A state transition management device includes a first terminal receiving a first signal based on a current state-number, a memory which stores a state transition rule and from which a plurality of subsequent state-number candidates are read out in accordance with the first signal, a plurality of first nodes revealing the plurality of subsequent state-number candidates, a second terminal receiving a second signal based on the current state-number, a selection method specifying unit which outputs a selection method specifying signal in accordance with the second signal, a second node revealing the selection method specifying signal, a event terminal receiving a event-signal based on an event, a third terminal receiving a third signal based on the current state-number, a selection circuit which selects a subsequent state-number from the plurality of subsequent number candidates in accordance with the event-signal and the third signal.

Abstract: A semiconductor integrated circuit includes: a plurality of the functional blocks; a plurality of configuration data memories in which a plurality of configuration data are stored; and a plurality of programmable switches configured to control connection between said plurality of functional blocks based on one of the plurality of configuration data which is stored in a common one of said plurality of configuration data memories.

Abstract: A state transition management device includes a memory that stores subsequent state number candidates for a current state number and a selection circuit that selects a subsequent state number from among the subsequent state number candidates that have been read out from the memory. For the state number having the subsequent state number candidates that are branch destinations of the current state number and are small in number, the memory stores the subsequent state number candidates for a plurality of current state numbers at one address in the memory that can be concurrently read out. The selection circuit selects the subsequent state number based on an event identification code (109, 110) and a current state number.

Abstract: A reconfigurable integrated circuit includes a plurality of function blocks and a plurality of programmable switches to switchably connect between function blocks included in the plurality of function blocks. The plurality of function blocks each includes at least one operation unit or one memory unit. The plurality of function blocks each includes at least one data input port connected to at least on of the plurality of programmable switches and at least one data output port connected to at least one of the plurality of programmable switches. Further, at least a pair of function blocks included in the plurality of function blocks is connected without intervening the programmable switch and data being output from a direct output port included in one of the pair of function blocks can be input to a direct input port included in the other of the pair of function blocks.

Abstract: A semiconductor integrated circuit includes: a plurality of the functional blocks; a plurality of configuration data memories in which a plurality of configuration data are stored; and a plurality of programmable switches configured to control connection between said plurality of functional blocks based on one of the plurality of configuration data which is stored in a common one of said plurality of configuration data memories.

Abstract: Disclosed is a reconfigurable device including at least a bus that mutually connects functional blocks, a configuration information memory disposed corresponding to each of the functional blocks, an error detection circuit that detects an error in the configuration information memory, and a buffer which is on-off controlled based on information stored in the configuration information memory and each of which controls connection between each of the functional blocks and each bus. When an error in the configuration information memory is detected by the error detection circuit, the buffer with an output thereof connected to the bus is set to an off-state, based on a result of error detection.

Abstract: A state transition management device includes a memory that stores subsequent state number candidates for a current state number and a selection circuit that selects a subsequent state number from among the subsequent state number candidates that have been read out from the memory. For the state number having the subsequent state number candidates that are branch destinations of the current state number and are small in number, the memory stores the subsequent state number candidates for a plurality of current state numbers at one address in the memory that can be concurrently read out. The selection circuit selects the subsequent state number based on an event identification code (109, 110) and a current state number.

Abstract: Disclosed is a reconfigurable device including at least a bus that mutually connects functional blocks, a configuration information memory disposed corresponding to each of the functional blocks, an error detection circuit that detects an error in the configuration information memory, and a buffer which is on-off controlled based on information stored in the configuration information memory and each of which controls connection between each of the functional blocks and each bus. When an error in the configuration information memory is detected by the error detection circuit, the buffer with an output thereof connected to the bus is set to an off-state, based on a result of error detection.

Abstract: A reconfigurable integrated circuit includes a plurality of function blocks and a plurality of programmable switches to switchably connect between function blocks included in the plurality of function blocks. The plurality of function blocks each includes at least one operation unit or one memory unit. The plurality of function blocks each includes at least one data input port connected to at least on of the plurality of programmable switches and at least one data output port connected to at least one of the plurality of programmable switches. Further, at least a pair of function blocks included in the plurality of function blocks is connected without intervening the programmable switch and data being output from a direct output port included in one of the pair of function blocks can be input to a direct input port included in the other of the pair of function blocks.