Patents by Inventor Toshitada Netsu

Toshitada Netsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7518233
    Abstract: A sealing structure for multi-chip modules stable in cooling performance and excelling in sealing reliability is to be provided. The under face of a frame 5 compatible with a wiring board 1 in thermal expansion rate is fixed with solder 8 to the face of the wiring board 1 for mounting semiconductor devices 2; a rubber O-ring 15 is placed between the upper face of the frame 5 and the under face of the circumference of an air-cooled: heat sink 7; the plastic member 6 making possible relative sliding is placed between the upper face of the circumference of the heat sink 7 and the upper frame 10; the upper face of a plastic member 6 is restrained with the inside middle stage of an upper frame 10; and the lower part of the upper frame 10 and the frame 5 are fastened together with bolts 9.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: April 14, 2009
    Assignees: Hitachi, Ltd., Hitachi Information Technology Co., Ltd.
    Inventors: Kouichi Takahashi, Kenichi Kasai, Takahiro Daikoku, Takayuki Uda, Toshitada Netsu, Takeshi Yamaguchi, Takahiko Matsushita, Osamu Maruyama
  • Patent number: 6890799
    Abstract: According to the invention, a sealing top plate in a multi-chip module is formed from a ceramic with high thermal conductivity having a thermal expansion coefficient consistent with that of a multi-layer circuit substrate. A cooling flow path cover covering the entirety of cooling flow path grooves is formed as a separate metallic member. The back surface of the sealing top plate, on which are formed the cooling flow path grooves, is bonded directly to the back surface of a semiconductor device using solder. A thermal-conductive jacket with low thermal resistance is provided. A multi-chip module sealing frame is soldered to the edge of the sealing top plate. Furthermore, a sealing material such as an O-ring is simply interposed between the edge of the sealing top plate and the cooling water path cover, and tightening means is used to tighten the metallic cooling flow path cover and the multi-chip module sealing frame to each other.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: May 10, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Daikoku, Kenichi Kasai, Toshitada Netsu, Koichi Koyano, Takayuki Uda
  • Publication number: 20030103333
    Abstract: According to the invention, a sealing top plate in a multi-chip module is formed from a ceramic with high thermal conductivity having a thermal expansion coefficient consistent with that of a multi-layer circuit substrate. A cooling flow path cover covering the entirety of cooling flow path grooves is formed as a separate metallic member. The back surface of the sealing top plate, on which are formed the cooling flow path grooves, is bonded directly to the back surface of a semiconductor device using solder. A thermal-conductive jacket with low thermal resistance is provided. A multi-chip module sealing frame is soldered to the edge of the sealing top plate. Furthermore, a sealing material such as an O-ring is simply interposed between the edge of the sealing top plate and the cooling water path cover, and tightening means is used to tighten the metallic cooling flow path cover and the multi-chip module sealing frame to each other.
    Type: Application
    Filed: January 7, 2003
    Publication date: June 5, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Takahiro Daikoku, Kenichi Kasai, Toshitada Netsu, Koichi Koyano, Takayuki Uda
  • Patent number: 6528878
    Abstract: According to the invention, a sealing top plate in a multi-chip module is formed from a ceramic with high thermal conductivity having a thermal expansion coefficient consistent with that of a multi-layer circuit substrate. A cooling flow path cover covering the entirety of cooling flow path grooves is formed as a separate metallic member. The back surface of the sealing top plate, on which are formed the cooling flow path grooves, is bonded directly to the back surface of a semiconductor device using solder. A thermal-conductive jacket with low thermal resistance is provided. A multi-chip module sealing frame is soldered to the edge of the sealing top plate. Furthermore, a sealing material such as an O-ring is simply interposed between the edge of the sealing top plate and the cooling water path cover, and tightening means is used to tighten the metallic cooling flow path cover and the multi-chip module sealing frame to each other.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: March 4, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Daikoku, Kenichi Kasai, Toshitada Netsu, Koichi Koyano, Takayuki Uda
  • Patent number: 6272020
    Abstract: A semiconductor device-mounting substrate is provided with a semiconductor device, a capacitor device, and a wiring substrate. The wiring substrate has a space in which the capacitor device should be located, and the capacitor device is locate in the space. Terminals of a driving power supply wiring for the semiconductor device are provided on a surface of the space, and the terminals are connected with the capacitor device.
    Type: Grant
    Filed: October 15, 1998
    Date of Patent: August 7, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hiromi Tosaki, Takaji Takenaka, Kazutoshi Takahashi, Norio Sengoku, Toshitada Netsu
  • Patent number: 5151773
    Abstract: An electronic circuit apparatus in which electronic circuit components are mounted to multiwiring substrate or the like for use with electronic circuits such as an LSI are sealed airtight by sealing units. The sealing unit is sealed by an upper board designated as an upper board sealing unit and a side board designated as a side board sealing unit, and the shape of the edge on cross section of the side board is convex or circular. Metallization is applied to solder joint portions between a substrate and a side board and between the side board and the upper board, and a predetermined solder joint height is provided by a support post to effect solder joining.
    Type: Grant
    Filed: March 28, 1991
    Date of Patent: September 29, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoshi Matsui, Ryohei Satoh, Toshitada Netsu, Hideaki Sasaki, Mitugu Shirai, Kenichi Hamamura
  • Patent number: 5136360
    Abstract: An electronic circuit device comprising an electronic part having a gold-plated connecting terminal arranged thereon connected through a solder to a circuit substrate on the predetermined connecting element thereof, in which the connecting terminal of the electronic part and the solder-connected portion of the circuit substrate are constituted by an alloy composition consisting of 1.0 to 8.0 wt. % of Ag, 0.1 to 6.0 wt % of Au and the balance of Sn, is provided. The device is made by using a solder for use in connecting a gold-plated connecting terminal which consists of 1.0 to 8.
    Type: Grant
    Filed: August 6, 1990
    Date of Patent: August 4, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Masahide Harada, Ryohei Satoh, Fumiyuki Kobayashi, Takaji Takenaka, Toshitada Netsu, Hideaki Sasaki, Mitugu Shirai