Patents by Inventor Toshitaka Hara

Toshitaka Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9078358
    Abstract: A substrate (1) includes conductive portions (7) formed by press working and a resin portion (11) integrally injection-molded with the conductive portions (7). The conductive portions (7) are formed from, for example, a copper alloy. The resin portion 11 is formed from, for example, PPS. A surface-mount component (3), which is an electronic surface-mount component, is mounted on the substrate (1). The surface-mount component (3) has electrodes (5) at its opposite sides, and the electrodes (5) and the respective conductive portions (7) are electrically connected by means of a solder (9). The substrate (1) has a hole (13), which functions as a stress relaxation mechanism, formed in the resin portion (11) (a portion extending therethrough) between connection portions (15) under the surface-mount component (3). The substrate (1) also has resin-exposed portions (13), which function as a stress relaxation mechanism, formed on opposite sides of the surface-mount component (3).
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 7, 2015
    Assignees: FURUKAWA ELECTRIC CO., LTD., FURUKAWA AUTOMOTIVE SYSTEMS, INC
    Inventors: Tomoaki Toratani, Toshitaka Hara, Kyutaro Abe, Motomu Shibamura, Kyosuke Hashimoto
  • Publication number: 20120267152
    Abstract: A substrate usable for such as DC-DC converters, which has no defects such as openings therein but is more compact and easy to be manufactured and a method of manufacturing the same is provided. First, circuit materials are cut off by pressing and bended to be formed in desired shapes. Next, the circuit materials are joined or placed in predetermined positions to form a circuit conductor 15. Junction is performed by welding. Next, the circuit conductor 15 is installed on the mold 19. The mold 19 is for injection molding of resin 9 and has a predetermined cavity therein. The circuit conductor 15 is fixed to the mold 19, for example by a pin of a prescribed position. In such a condition, resin is injected into a mold. The substrate 1 is formed by the injection of resin to a surface and between layers of the circuit conductor.
    Type: Application
    Filed: July 2, 2012
    Publication date: October 25, 2012
    Applicants: FURUKAWA AUTOMOTIVE SYSTEMS INC., FURUKAWA ELECTRIC CO., LTD.
    Inventors: Toshitaka HARA, Tomoaki TORATANI, Kyutaro ABE, Koichi MAENO, Motomu SHIBAMURA
  • Publication number: 20120255767
    Abstract: A substrate (1) includes conductive portions (7) formed by press working and a resin portion (11) integrally injection-molded with the conductive portions (7). The conductive portions (7) are formed from, for example, a copper alloy. The resin portion 11 is formed from, for example, PPS. A surface-mount component (3), which is an electronic surface-mount component, is mounted on the substrate (1). The surface-mount component (3) has electrodes (5) at its opposite sides, and the electrodes (5) and the respective conductive portions (7) are electrically connected by means of a solder (9). The substrate (1) has a hole (13), which functions as a stress relaxation mechanism, formed in the resin portion (11) (a portion extending therethrough) between connection portions (15) under the surface-mount component (3). The substrate (1) also has resin-exposed portions (13), which function as a stress relaxation mechanism, formed on opposite sides of the surface-mount component (3).
    Type: Application
    Filed: June 18, 2012
    Publication date: October 11, 2012
    Applicants: FURUKAWA AUTOMOTIVE SYSTEMS, INC., FURUKAWA ELECTRIC CO., LTD.
    Inventors: Tomoaki TORATANI, Toshitaka HARA, Kyutaro ABE, Motomu SHIBAMURA, Kyosuke HASHIMOTO
  • Publication number: 20020006742
    Abstract: An electrical connection box 1 having circuit boards 41, 42 contained in a case. The circuit boards 41, 42 are assigned to a power supply system for start and travelling of an automobile and a power supply system for general loads, respectively.
    Type: Application
    Filed: November 29, 1999
    Publication date: January 17, 2002
    Applicant: THE FURUKAWA ELECTRIC CO., LTD.
    Inventors: TOSHITAKA HARA, HISAO HONMA, YUTAKA MATSUDA, JUTARO MUKAI, MITSUO TANAKA
  • Patent number: 6127741
    Abstract: A vehicular use power feed apparatus comprising a battery and a plurality of power distribution units connected in a loop via power feed lines. Each power distribution unit has a current monitoring circuit, a current amount determination circuit, and a current direction determination circuit, detects the direction of current and magnitude of current flowing through the power feed line, and thereby detects an occurrence of a short-circuit. A control unit exchanges information regarding occurrence of short-circuits with adjoining power distribution units via a multiplex signal transmission unit so as to pinpoint the trouble point. The control unit operates the relay switch circuits on the two sides to break the connection so as to isolate the trouble point in cooperation with the control unit of the adjoining power distribution unit. The other relay switch circuit is operated to establish a connection so as to establish a new power feed line.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: October 3, 2000
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Yutaka Matsuda, Toshitaka Hara, Takezo Sugimura, Satoshi Kawai
  • Patent number: 5490143
    Abstract: When a message is transmitted, frame by frame, from any one (10) of a plurality of multiplex nodes to a common multiplex bus (MB) to which the multiplex nodes are connected, each of the multiplex nodes (20 and 30) determines that transmission of a frame therefrom is allowed when it detects a transmission permission signal (b, b') added to the frame after detection of and idle state of the multiplex bus, and starts transmitting a message data frame. This makes it possible to properly implement priority-based control according to the priority levels of the data frames irrespectively of variations in the reference clocks of the multiplex nodes. Further, receiving multiplex nodes perform frame synchronization at the rise of a special code (a) of a start code (SOM) of a message data frame, and then perform re-synchronization at the rise of a special bit pattern (b") which includes a passive bit and a dominant bit.
    Type: Grant
    Filed: May 10, 1994
    Date of Patent: February 6, 1996
    Assignees: The Furukawa Electric Co., Ltd, Mazda Motor Corp.
    Inventors: Toshitaka Hara, Yutaka Matsuda, Kyosuke Hashimoto, Hiroo Moriue, Yoshikazu Nobutoki, Hiroaki Sakamoto, Koji Terayama, Hideki Nakazono
  • Patent number: 5133067
    Abstract: When a user of a data base desires to fetch necessary information from the data base, display the fetched information on a display unit and save a part of the data displayed on the screen of the display unit, partial data on the display screen is extracted on the basis of two kinds of tables, a character string table and a range table. The character string table is for defining a character string used as a key to search for the data on the display screen. When a character string is found on the display screen, the range table is applied to determine a data region to be extracted inclusive of this character string. The character string used as a key to search and the extracting data region which are defined in advance on the respective tables simplify the operation by the user.
    Type: Grant
    Filed: October 6, 1986
    Date of Patent: July 21, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Toshitaka Hara, Kazuhiro Fujisaki
  • Patent number: 4307393
    Abstract: A cathode ray tube having a viewing screen on which time points represented by a plurality of points spaced from one another with a predetermined time interval are displayed in the raster direction, while display quantities of trend graphs are displayed as functions of the time points in the direction perpendicular to the raster direction by a plurality of points spaced from one another with a predetermined interval. A raster scanning is effected by sweeping the viewing screen with a scanning point whereby the scanning lines thus produced are correlated to the spaced points representing the display quantities. Apparatus stores the display quantities of the trend graph corresponding to the time points, sequentially reads out the display quantities from the memory apparatus in the order of the time points, and compares the display quantities read out from the memory apparatus with a display quantity represented by an instant scan line.
    Type: Grant
    Filed: November 9, 1978
    Date of Patent: December 22, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Nagaharu Hamada, Toshitaka Hara, Mitsuo Kikkawa, Yukitaka Hayashi
  • Patent number: 4237543
    Abstract: A display system for displaying information in response to an input video signal comprises a data control unit including a microprocessor and a microprogram memory for storing a program for the microprocessor, a refresh memory unit connected to the data control unit through an address bus and a data bus, and a video control unit for accessing display data stored in the refresh memory unit by a timing control unit to produce a video signal. The refresh memory unit comprises memories sectioned by byte, an I/O controller which receives a read/write control signal to indicate whether the access by the data control unit is read access or write access and an access memory specifying signal to indicate whether it is a one-byte memory access or a two-byte memory access to produce an I/O control signal, and a memory controller responsive to the I/O control signal to control data access to the two byte memories.
    Type: Grant
    Filed: September 1, 1978
    Date of Patent: December 2, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Yoji Nishio, Toshitaka Hara, Nagaharu Hamada
  • Patent number: 4231032
    Abstract: A graph display apparatus using a CRT display unit of raster scanning type for displaying a graph with a high accuracy, that is, a high resolution. The apparatus comprises a raster counter for counting the number of rasters to identify the raster number of the scanning lines presently scanning the display screen of the CRT display unit, and a plurality of graph display units for displaying a graph with a standard accuracy.
    Type: Grant
    Filed: September 7, 1978
    Date of Patent: October 28, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Toshitaka Hara, Nagaharu Hamada
  • Patent number: 4200869
    Abstract: A data display control system for displaying respective data memorized in a plurality of refresh memories which is operable in various display modes including a selective picture display, a superimposed picture display and a shifting picture display. Individual data memorized in respective refresh memories contain each a display control bit adapted to determine whether or not the individual data are to be displayed on the screen. The data display control system reads out from the respective refresh memories a data information to be picture-displayed and only when the contents of a display control bit contained in the data information designate a display, it converts this data information into a video signal for a picture display. The contents of the display control bit are changeable for individual data.
    Type: Grant
    Filed: February 14, 1978
    Date of Patent: April 29, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Norio Murayama, Yukitaka Hayashi, Nagaharu Hamada, Toshitaka Hara
  • Patent number: 4156904
    Abstract: A computer system comprises a central processor unit, a single memory apparatus and an external processor unit which is adapted to read out N bytes of data in each period of T.sub.o. The number n of data remaining to be processed after a time elapse T.sub.1 (T.sub.1 < T.sub.o) from the beginning of the period T.sub.o is successively compared with the number m of data which can be read out continuously by the external processor unit during a remaining time span (T.sub.o -T.sub.1). So long as the number n is smaller than the number m the external processor unit is allowed to read out the data from the memory apparatus only when the central processor unit is not using the memory apparatus. On the other hand, when the number n becomes equal to the number m, connection between the memory apparatus and the central unit is interrupted to allow in turn the external processor unit to read out data from the memory apparatus, whereby the processing efficiency of the computer system is improved.
    Type: Grant
    Filed: August 23, 1977
    Date of Patent: May 29, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Yasuo Minowa, Toshitaka Hara, Nagaharu Hamada
  • Patent number: 4129859
    Abstract: A raster scan type CRT display system is disclosed which has a randomly accessable refresh memory. The display system comprises column and row start address registers for defining a read start address for the refresh memory, column and row address counters for counting the contents of the column and row start address registers as start positions to generate a read address of the refresh memory for display, column and row cursor registors for defining a data entry position on a CRT screen, and column and row address generators for generating an entry address for the refresh memory based on the contents of the column and row start address registers and the contents of the column and row cursor registers, whereby a rolling or shifting of the image is effected and the refresh memory can be accessed by a processor for read/write operation without the need to monitor the image rolling.
    Type: Grant
    Filed: February 8, 1977
    Date of Patent: December 12, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Nagaharu Hamada, Toshitaka Hara, Nobuo Sato
  • Patent number: 4129858
    Abstract: A system for controlling display of characters on partitioned regions of a CRT display surface comprising a refresh memory having a capacity enough to store application display data for exhibiting application display on the entire area of the CRT display surface, and a special display data memory storing special display data for exhibiting special display on a limited specific region, for example, the lowest and second lowest display line portions of the CRT display surface to be pointed by a light pen.
    Type: Grant
    Filed: March 23, 1977
    Date of Patent: December 12, 1978
    Assignee: Hitachi, Ltd.
    Inventor: Toshitaka Hara
  • Patent number: 3947818
    Abstract: A bus-coupler or bus window in an information transport system for connecting a plurality of buses, to each of which a plurality of arithmetic units, a plurality of memory or storage units and a plurality of input-output units are connected separately through stations. The bus coupler includes a dead-lock control circuit for preventing a dead-lock which could possibly occur in communication between the buses.
    Type: Grant
    Filed: December 9, 1974
    Date of Patent: March 30, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiki Kobayashi, Tadaaki Bandoh, Toshitaka Hara