Patents by Inventor Toshitaka Kanemaru

Toshitaka Kanemaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490638
    Abstract: A semiconductor device may include: a semiconductor substrate; a surface electrode covering a surface of the semiconductor substrate; an insulating protection film covering a part of a surface of the surface electrode; and a solder-bonding metal film, the solder-bonding metal film covering a range spreading from a surface of the insulating protection film to the surface of the surface electrode, wherein the surface electrode may include: a first metal film provided on the semiconductor substrate; a second metal film being in contact with a surface of the first metal film, and having tensile strength higher than tensile strength of the first metal film; and a third metal film being in contact with a surface of the second metal film, and having tensile strength which is lower than the tensile strength of the second metal film and is higher than the tensile strength of the first metal film.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: November 26, 2019
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Takashi Kuno, Hiroki Tsuma, Satoshi Kuwano, Akitaka Soeno, Toshitaka Kanemaru, Kenta Hashimoto, Noriyuki Kakimoto, Shuji Yoneda
  • Patent number: 10115798
    Abstract: A semiconductor device is provided with: a semiconductor substrate; a first electrode disposed on a surface of the semiconductor device and configured to be soldered to a conductive member; and a second electrode disposed on the surface of the semiconductor device and configured to be wire-bonded to a conductive member. The first electrode includes first, second and third metal layers. The second metal layer is located between the first and third metal layers. A metallic material of the second metal layer is greater in tensile strength than a metallic material of each one of the first metal layer and the third metal layer. The second electrode includes a layer made of a same metallic material as one of the first metal layer and the third metal layer, and does not include any layers made of a same metallic material as the second metal layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 30, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naoki Akiyama, Hiroki Tsuma, Takashi Kuno, Toshitaka Kanemaru, Kenta Hashimoto
  • Publication number: 20180233571
    Abstract: A semiconductor device is provided with: a semiconductor substrate; a first electrode disposed on a surface of the semiconductor device and configured to be soldered to a conductive member; and a second electrode disposed on the surface of the semiconductor device and configured to be wire-bonded to a conductive member. The first electrode includes first, second and third metal layers. The second metal layer is located between the first and third metal layers. A metallic material of the second metal layer is greater in tensile strength than a metallic material of each one of the first metal layer and the third metal layer. The second electrode includes a layer made of a same metallic material as one of the first metal layer and the third metal layer, and does not include any layers made of a same metallic material as the second metal layer.
    Type: Application
    Filed: January 30, 2018
    Publication date: August 16, 2018
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Naoki AKIYAMA, Hiroki TSUMA, Takashi KUNO, Toshitaka KANEMARU, Kenta HASHIMOTO
  • Publication number: 20180212028
    Abstract: A semiconductor device may include: a semiconductor substrate; a surface electrode covering a surface of the semiconductor substrate; an insulating protection film covering a part of a surface of the surface electrode; and a solder-bonding metal film, the solder-bonding metal film covering a range spreading from a surface of the insulating protection film to the surface of the surface electrode, wherein the surface electrode may include: a first metal film provided on the semiconductor substrate; a second metal film being in contact with a surface of the first metal film, and having tensile strength higher than tensile strength of the first metal film; and a third metal film being in contact with a surface of the second metal film, and having tensile strength which is lower than the tensile strength of the second metal film and is higher than the tensile strength of the first metal film.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 26, 2018
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Takashi KUNO, Hiroki TSUMA, Satoshi KUWANO, Akitaka SOENO, Toshitaka KANEMARU, Kenta HASHIMOTO, Noriyuki KAKIMOTO, Shuji YONEDA
  • Patent number: 9865728
    Abstract: A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: January 9, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka Soeno, Masaru Senoo, Takashi Kuno, Satoshi Kuwano, Noriyuki Kakimoto, Toshitaka Kanemaru, Kenta Hashimoto, Yuma Kagata
  • Publication number: 20170263754
    Abstract: A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.
    Type: Application
    Filed: February 6, 2017
    Publication date: September 14, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Akitaka SOENO, Masaru SENOO, Takashi KUNO, Satoshi KUWANO, Noriyuki KAKIMOTO, Toshitaka KANEMARU, Kenta HASHIMOTO, Yuma KAGATA
  • Publication number: 20050023644
    Abstract: In the manufacturing process of a Bi-CMOS semiconductor device, which includes a CMOSFET and a bipolar transistor, the steps for forming a well region, source regions, and drain regions of the CMOSFET are also used for forming the bipolar transistor. One of the steps is used for introducing impurities of the same conductivity type in a surface of a base region of the bipolar transistor in order to form a high impurity concentration region in the surface. The high impurity concentration region is formed such that the distance between an emitter region of the bipolar transistor and the high impurity concentration region becomes 1 to 2 ?m. The shift in device characteristics of the bipolar transistor is improved by the high impurity concentration region even if the impurity concentration is relatively low at the surface of the base region of the bipolar transistor.
    Type: Application
    Filed: August 31, 2004
    Publication date: February 3, 2005
    Inventors: Takuya Okuno, Shoji Mizuno, Toshitaka Kanemaru
  • Patent number: 6803634
    Abstract: In the manufacturing process of a Bi-CMOS semiconductor device, which includes a CMOSFET and a bipolar transistor, the steps for forming a well region, source regions, and drain regions of the CMOSFET are also used for forming the bipolar transistor. One of the steps is used for introducing impurities of the same conductivity type in a surface of a base region of the bipolar transistor in order to form a high impurity concentration region in the surface. The high impurity concentration region is formed such that the distance between an emitter region of the bipolar transistor and the high impurity concentration region becomes 1 to 2 &mgr;m. The shift in device characteristics of the bipolar transistor is improved by the high impurity concentration region even if the impurity concentration is relatively low at the surface of the base region of the bipolar transistor.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: October 12, 2004
    Assignee: Denso Corporation
    Inventors: Takuya Okuno, Shoji Mizuno, Toshitaka Kanemaru
  • Publication number: 20030085414
    Abstract: In the manufacturing process of a Bi-CMOS semiconductor device, which includes a CMOSFET and a bipolar transistor, the steps for forming a well region, source regions, and drain regions of the CMOSFET are also used for forming the bipolar transistor. One of the steps is used for introducing impurities of the same conductivity type in a surface of a base region of the bipolar transistor in order to form a high impurity concentration region in the surface. The high impurity concentration region is formed such that the distance between an emitter region of the bipolar transistor and the high impurity concentration region becomes 1 to 2 &mgr;m. The shift in device characteristics of the bipolar transistor is improved by the high impurity concentration region even if the impurity concentration is relatively low at the surface of the base region of the bipolar transistor.
    Type: Application
    Filed: November 7, 2002
    Publication date: May 8, 2003
    Inventors: Takuya Okuno, Shoji Mizuno, Toshitaka Kanemaru