Abstract: In a layout design of a printed circuit board, more accurate bypass capacitor arrangement that has taken into consideration a wiring within a package of an IC is implemented. An information processing apparatus according to the present invention includes: a die pad specifying unit configured to specify a power source pad of a die and a ground pad of the die from design information on a printed circuit board; a bypass capacitor specifying unit configured to specify a bypass capacitor that is arranged on the printed circuit board from the design information; and a unit configured to derive an evaluation value for evaluating the arrangement of the specified bypass capacitor based on the design information, information on the specified power source pad of the die and ground pad of the die, and information on the specified bypass capacitor.

Abstract: In a layout design of a printed circuit board, more accurate bypass capacitor arrangement that has taken into consideration a wiring within a package of an IC is implemented. An information processing apparatus according to the present invention includes: a die pad specifying unit configured to specify a power source pad of a die and a ground pad of the die from design information on a printed circuit board; a bypass capacitor specifying unit configured to specify a bypass capacitor that is arranged on the printed circuit board from the design information; and a unit configured to derive an evaluation value for evaluating the arrangement of the specified bypass capacitor based on the design information, information on the specified power source pad of the die and ground pad of the die, and information on the specified bypass capacitor.

Abstract: Design information including layout information of a print circuit board associated with an electronic equipment, and component information is acquired, and a verification condition associated with crosstalk noise is input. Information of signal lines which should verify influence of the crosstalk noise are extracted from the design information. Based on the verification condition, a signal line, which crosses or overlaps a signal line other than the signal line corresponding to the extracted information planerly viewed from a laminating direction of layers of the print circuit board, of the signal lines corresponding to the extracted information is detected as a victim wiring.

Abstract: Layout information indicating a layout of circuits on a print circuit board is obtained. With reference to the layout information, a connection portion, which electrically connects a ground pattern of the print circuit board and an external ground of the print circuit board, is specified, and a pin, which is included in a connector laid out on the print circuit board and is connected to the ground pattern, is identified. Then, a discharge route between the pin and connection portion is determined.

Abstract: Layout information indicating a layout of circuits on a print circuit board is obtained. With reference to the layout information, a connection portion, which electrically connects a ground pattern of the print circuit board and an external ground of the print circuit board, is specified, and a pin, which is included in a connector laid out on the print circuit board and is connected to the ground pattern, is identified. Then, a discharge route between the pin and connection portion is determined.