Patents by Inventor Toshitaka Nonaka

Toshitaka Nonaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6444255
    Abstract: An electrode substrate is brush cleaned with a hydrogen gas dissolved water, which has an oxidation-reduction potential of −860 mV to −400 mV and a pH of 8 to 12, before applying an alignment layer material on the electrode substrate. Thus, it is possible to decrease the manufacturing costs without decreasing the detergency.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: September 3, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Nagahara, Naoya Hayamizu, Naoaki Sakurai, Noriko Okoshi, Toshitaka Nonaka, Hiroaki Furuya
  • Publication number: 20010012544
    Abstract: An electrode substrate is brush cleaned with a hydrogen gas dissolved water, which has an oxidation-reduction potential of −860 mV to −400 mV and a pH of 8 to 12, before applying an alignment layer material on the electrode substrate. Thus, it is possible to decrease the manufacturing costs without decreasing the detergency.
    Type: Application
    Filed: February 13, 2001
    Publication date: August 9, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiyuki Nagahara, Naoya Hayamizu, Naoaki Sakurai, Noriko Okoshi, Toshitaka Nonaka, Hiroaki Furuya
  • Patent number: 6210748
    Abstract: An electrode substrate is brush cleaned with a hydrogen gas dissolved water, which has an oxidation-reduction potential of −860 mV to −400 mV and a pH of 8 to 12, before applying an alignment layer material on the electrode substrate. Thus, it is possible to decrease the manufacturing costs without decreasing the detergency.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: April 3, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Nagahara, Naoya Hayamizu, Naoaki Sakurai, Noriko Okoshi, Toshitaka Nonaka, Hiroaki Furuya
  • Patent number: 6036568
    Abstract: On the surface of an array substrate 60, a sealing material 64 is provided so as to surround a display region, and a plurality of spacers 66 are provided in the display region. The array substrate 60 and a counter substrate 62 are vacuum held to stages 20 and 18, respectively, so that the array substrate 60 and the counter substrate 62 face each other. In one of the stages, a recessed portion 26 facing the effective region of the counter substrate 62 is formed. By evacuating the recessed portion, the effective region of the counter substrate 62 is deflected so as to go away from the effective region of the array substrate 60. In this state, the peripheral portions of the array substrate 60 and the counter substrate 62 are panel aligned with each other via the sealing material 64. Subsequently, the counter substrate 62 is positioned with respect to the array substrate 60 by means of an X-Y-.theta. stage.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: March 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsunori Murouchi, Satoru Narioka, Tetsuya Nishino, Hirokazu Morimoto, Takaomi Tanaka, Tadashi Honda, Hiroshi Otaguro, Hironori Takabayashi, Toshitaka Nonaka