Abstract: This image pickup apparatus is capable of picking up very low level images, such as a star or a comet in a night sky, and is capable of obtaining a video signal having a desired S/N ratio without using a conventional noise reducer. The apparatus comprises a television camera including an image pickup tube, a field memory for storing a video signal delivered from the television camera, and a write-inhibiting control circuit, wherein a period of beam scanning for generating the video signal in the image pickup tube is extended to n-times the standard field period for increasing the sensitivity of the image pickup tube. Writing to the field memory is inhibited in other periods except for the beam scanning period, while a normal television signal is continuously obtained from the field memory. A key signal corresponding to dark portions of the image that are not to be enhanced may be generated and stored in an area memory, and then read out from the area memory during every standard field period.

Abstract: A television video signal synchronizing apparatus, which synchronizes an input television video signal to a reference timing mark. The input video signal is digitized and stored in a memory at locations which are provided by a writing address generator. The writing operation is performed in synchronism with the input video signal. A reading address generator produces reading addresses for reading out the stored video signal to deliver an output television signal which is synchronized to the reference timing mark. The reading address generator is controlled to read out an active video portion of the stored video signal after a delay of about one horizontal scanning period (63.5 microseconds in the NTSC system) immediately after the writing operation of the same active video portion. Thereby "lip lag" i.e. a mismatch between the audio and video signals, is avoided.

Abstract: A television synchronizing apparatus for synchronizing an input television signal to a reference television signal. The input and output television signals are of the type which include several signal components including a video signal, a color subcarrier signal and a horizontal sync signal. The input television signal is stored in a memory at locations thereof which are determined by write-in memory addresses which are produced in synchronism with the input television signal. The input television signal is read-out or retrieved from the memory under the control of read out addresses which are produced in synchronism with the reference television signal.

Abstract: A digital audio synchronizing system resynchronizes the audio signal of a video signal by storing the audio signal in a memory and reading it out from the memory after a time period which is related to the time by which the video signal is delayed as a result of being synchronized to a reference video signal. In order to prevent a discontinuity in the audio signal waveform caused by variations in the time difference between the video signal and the reference signal, the digital audio signal is read out from memory addresses which correspond to the previous difference time and also to a new updated difference time value. The two outputs which are generated by reading the signal from two different areas of the memory are cross-faded with one another over a predetermined time period. The cross-fade operation can be repeated over several cycles, each taking a predetermined unit of time until the audio signal is synchronized to its video counterpart.

Abstract: A digital audio synchronizing system resynchronizes the audio signal of a video signal by storing the audio signal in a memory and reading it out from the memory after a time period which is related to the time by which the video signal is delayed as a result of being synchronized to a reference video signal. In order to prevent a discontinuity in the audio signal waveform caused by variations in the video delay between the video signal and the reference signal, the digital audio signal is read out as a first and a second output from memory addresses which correspond to the previous video delay and to a new updated video delay value. A synchronized audio signal is obtained by switching from the first output to the second output when the muting times of the first and the second outputs are coincident with each other.

Abstract: In an error correction circuit of the type in which a received audio signal is passed to the error correction output when no error is detected and wherein a substitute signal, e.g. either a previous value of the received audio signal or a muting signal, is provided to the error correction circuit output when an error is detected in the received audio signal, complementary gain control circuits are employed to gradually fade in the newly selected signal while gradually fading out the previously selected signal to eliminate undesirable clicking noise.

Abstract: The invention provides a color framing circuit for a digital memory, which has a first read line flip-flop generator for producing an RLFF.sub.0 pulse; a toggle flip-flop for receiving a loading data from a memory using a vertical pulse or a delayed (1H) vertical pulse as a load timing pulse only when the RLFF.sub.0 pulse is high and for producing an output signal (RLFF.sub.1 pulse); a vertical selector for selecting one of the vertical pulse and the delayed vertical pulse when the output signal from the toggle flip-flop is high; a read address counter for producing an address signal; and a blanking/burst generator for receiving the RLFF.sub.0 and RLFF.sub.1 pulses as control pulses, thereby receiving as a read address signal the address signal from the address counter. An output video signal phase offset is decreased corresponding to a range of 140 ns (peak-to-peak), and one of the address counters is eliminated.

Abstract: A digital television video signal storage system wherein the required memory capacity is reduced and memory utilization efficiency increased by reducing the number of bits in an imaginary vertical memory address without effectively increasing the number of bits in an imaginary horizontal address.

Abstract: A digital transmission system wherein a signal to be transmitted is represented by a plurality of parallel data bits, each of said data bits having a positional significance ranging from a most significant data bit to a least significant data bit. Each of said data bits are assigned to one of a plurality of data transmission highways based on the positional significance of the data bit. Failure of a particular highway results in a reassignment of the data bits to the highways so that transmission degradation is minimized.