Patents by Inventor Toshitake Seki
Toshitake Seki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10470300Abstract: A glass panel for a wiring board, includes a first surface and a second surface, the second surface being opposite to the first surface; and an alignment mark constituted by a plurality of through holes each penetrating the glass panel from the first surface to the second surface, at least one of the plurality of through holes being configured such that a first diameter “t1” of a first opening at the first surface, a second diameter “t2” of a second opening at the second surface, and a minimum diameter “t3” between the first surface and the second surface satisfy t1>t3 and also t2>t3.Type: GrantFiled: July 24, 2018Date of Patent: November 5, 2019Assignee: AGC Inc.Inventors: Toshitake Seki, Yutaka Takagi, Toshikazu Horio, Atsuhiko Sugimoto
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Patent number: 8546700Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.Type: GrantFiled: March 8, 2011Date of Patent: October 1, 2013Assignee: NGK Spark Plug Co., Ltd.Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Kazuhiro Hayashi, Jun Otsuka, Manabu Sato
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Patent number: 7973245Abstract: An intermediate board has a board core formed by a main core body and a sub-core portion. The main core body has a plate-like shape and includes an open sub-core housing portion in which the sub-core portion is housed. A first terminal array of the board core has an area that overlaps an orthogonal projection of the sub-core portion. The latter incorporates a laminated ceramic capacitor formed by first and second conductor layers with a ceramic (dielectric) layer therebetween. The first layer is connected to first and second side terminals of a first type while the second layer is connected to first and second side terminals of a second type. The housing portion has an inner edge which, in cross section, is of a quadrate shape, and a radius portion is formed at each corner having a dimension of between 0.1 and 2 mm.Type: GrantFiled: February 6, 2008Date of Patent: July 5, 2011Assignee: NGK Spark Plug Co., Ltd.Inventors: Masaki Muramatsu, Shinji Yuri, Kazuhiro Urashima, Hiroshi Yamamoto, Toshitake Seki, Motohiko Sato
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Publication number: 20110157763Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Applicant: NGK SPARK PLUG CO., LTD.Inventors: Hiroshi YAMAMOTO, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Kazuhiro Hayashi, Jun Otsuka, Manabu Sato
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Patent number: 7956454Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.Type: GrantFiled: June 1, 2009Date of Patent: June 7, 2011Assignee: NGK Spark Plug Co., Ltd.Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Akifumi Tosa
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Patent number: 7932471Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.Type: GrantFiled: August 4, 2006Date of Patent: April 26, 2011Assignee: NGK Spark Plug Co., Ltd.Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Kazuhiro Hayashi, Jun Otsuka, Manabu Sato
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Publication number: 20090255719Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.Type: ApplicationFiled: June 1, 2009Publication date: October 15, 2009Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Akifumi Tosa
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Patent number: 7580240Abstract: A via array capacitor including a capacitor body having a first main surface and a second main surface and having a structure in which dielectric layers and inner electrode layers are alternately laminated; a plurality of via conductors which conduct the inner electrode layers to each other and are, as a whole, arranged in array form; and metal-containing layers which are disposed on at least one of the first main surface and the second main surface, wherein a total volume of the inner electrode layers and the metal-containing layers included in the via array capacitor is from 45 vol.% to 95 vol.% of a volume of the via array capacitor.Type: GrantFiled: November 22, 2006Date of Patent: August 25, 2009Assignee: NGK Spark Plug Co., Ltd.Inventors: Hiroshi Yamamoto, Toshitake Seki, Jun Otsuka, Manabu Sato, Masahiko Okuyama
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Patent number: 7557440Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.Type: GrantFiled: August 24, 2006Date of Patent: July 7, 2009Assignee: NGK Spark Plug Co., Ltd.Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Akifumi Tosa
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Patent number: 7532453Abstract: In order to provide a built-in capacitor type wiring board capable of preventing misalignment of the capacitor, a capacitor built-in type wiring board is provided which includes a core board; a multilayer portion disposed on at least one side of the core board and formed by a plurality of interlayer insulating layers; and a plurality of conductor layers alternately laminated on the core board. The capacitor is of a chip-like shape with first and second main surfaces and includes a dielectric layer; electrode layers laminated on the dielectric layer; and a hole portion opening at least at the second main surface. The capacitor is embedded in the interlayer insulating layers so that the second main surface faces the core board.Type: GrantFiled: November 20, 2006Date of Patent: May 12, 2009Assignee: NGK Spark Plug Co., Ltd.Inventors: Hiroshi Yamamoto, Toshitake Seki, Yasuhiko Inui, Jun Otsuka, Manabu Sato
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Publication number: 20080223607Abstract: An intermediate board has a board core formed by a main core body and a sub-core portion. The main core body has a plate-like shape and includes an open sub-core housing portion in which the sub-core portion is housed. A first terminal array of the board core has an area that overlaps an orthogonal projection of the sub-core portion. The latter incorporates a laminated ceramic capacitor formed by first and second conductor layers with a ceramic (dielectric) layer therebetween. The first layer is connected to first and second side terminals of a first type while the second layer is connected to first and second side terminals of a second type. The housing portion has an inner edge which, in cross section, is of a quadrate shape, and a radius portion is formed at each corner having a dimension of between 0.1 and 2 mm.Type: ApplicationFiled: February 6, 2008Publication date: September 18, 2008Inventors: Masaki MURAMATSU, Shinji Yuri, Kazuhiro Urashima, Hiroshi Yamamoto, Toshitake Seki, Motohiko Sato
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Patent number: 7345246Abstract: An intermediate board has a board core formed by a main core body and a sub-core portion. The main core body has a plate-like shape and includes an open sub-core housing portion in which the sub-core portion is housed. A first terminal array of the board core has an area that overlaps an orthogonal projection of the sub-core portion. The latter incorporates a laminated ceramic capacitor formed by first and second conductor layers with a ceramic (dielectric) layer therebetween. The first layer is connected to first and second side terminals of a first type while the second layer is connected to first and second side terminals of a second type. The housing portion has an inner edge which, in cross section, is of a quadrate shape, and a radius portion is formed at each corner having a dimension of between 0.1 and 2 mm.Type: GrantFiled: February 9, 2006Date of Patent: March 18, 2008Assignee: NGK Spark Plug Co., Ltd.Inventors: Masaki Muramatsu, Shinji Yuri, Kazuhiro Urashima, Hiroshi Yamamoto, Toshitake Seki, Motohiko Sato
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Publication number: 20070121273Abstract: In order to provide a built-in capacitor type wiring board capable of preventing misalignment of the capacitor, a capacitor built-in type wiring board is provided which includes a core board; a multilayer portion disposed on at least one side of the core board and formed by a plurality of interlayer insulating layers; and a plurality of conductor layers alternately laminated on the core board. The capacitor is of a chip-like shape with first and second main surfaces and includes a dielectric layer; electrode layers laminated on the dielectric layer; and a hole portion opening at least at the second main surface. The capacitor is embedded in the interlayer insulating layers so that the second main surface faces the core board.Type: ApplicationFiled: November 20, 2006Publication date: May 31, 2007Inventors: Hiroshi Yamamoto, Toshitake Seki, Yasuhiko Inui, Jun Otsuka, Manabu Sato
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Publication number: 20070117338Abstract: A via array capacitor comprising: a capacitor body including a first main surface and a second main surface and having a structure in which dielectric layers and inner electrode layers are alternately laminated; a plurality of via conductors which conduct the inner electrode layers to each other and are, as a whole, arranged in array form; and metal-containing layers which are disposed on at least one of the first main surface and the second main surface, wherein a total of a thickness of the metal-containing layers disposed on the first main surface and a thickness of the metal-containing layers disposed on the second main surface is from 15% to 80% of an overall thickness of the via array capacitor.Type: ApplicationFiled: November 22, 2006Publication date: May 24, 2007Inventors: Hiroshi Yamamoto, Toshitake Seki, Jun Otsuka, Manabu Sato, Masahiko Okuyama
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Publication number: 20070045814Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.Type: ApplicationFiled: August 24, 2006Publication date: March 1, 2007Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Akifumi Tosa
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Publication number: 20070030628Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.Type: ApplicationFiled: August 4, 2006Publication date: February 8, 2007Inventors: Hiroshi Yamamoto, Toshitake Seki, Shinji Yuri, Masaki Muramatsu, Motohiko Sato, Kazuhiro Hayashi, Jun Otsuka, Manabu Sato
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Publication number: 20060175083Abstract: An intermediate board has a board core formed by a main core body and a sub-core portion. The main core body has a plate-like shape and includes an open sub-core housing portion in which the sub-core portion is housed. A first terminal array of the board core has an area that overlaps an orthogonal projection of the sub-core portion. The latter incorporates a laminated ceramic capacitor formed by first and second conductor layers with a ceramic (dielectric) layer therebetween. The first layer is connected to first and second side terminals of a first type while the second layer is connected to first and second side terminals of a second type. The housing portion has an inner edge which, in cross section, is of a quadrate shape, and a radius portion is formed at each corner having a dimension of between 0.1 and 2 mm.Type: ApplicationFiled: February 9, 2006Publication date: August 10, 2006Inventors: Masaki Muramatsu, Shinji Yuri, Kazuhiro Urashima, Hiroshi Yamamoto, Toshitake Seki, Motohiko Sato