Abstract: A pipelined computer comprises a plurality of stages. An instruction subsequent to an operation mode changing instruction is held in a predetermined stage according to a type of the operation mode changing instruction. For example, if the instruction is the one subsequent to an ICP (Instruction mode Change to Privilege) instruction, it is held in an instruction decode stage where a privilege exception is detected. If the instruction is the one subsequent to an ACS (Addressing mode Change to Secure) instruction, it is held in an address adding stage where an address computation is performed. Moreover, if the instruction is the one subsequent to an ACD (Addressing mode Change to Direct) instruction, they are held in an address translation stage where an address translation is performed. These holdings are released after the operation mode changing instruction is completed.

Abstract: A controller for controlling requests to memory, said requests involving executing in a computer system an instruction having a variable length operand, for use in a computer system for managing the main store in a page size of 2.sup.m byte units by on demand paring processing and for executing an instruction or an operation in not larger than 2.sup.m (n is larger than m) byte operand units includes a detector for detecting the presence of operand data on a same or single page by referencing the (n-m) most significant bits of the n least significant bits of an effective address which has been generated. If the detector has detected the presence of the operand data on the same page, the memory request is altered by dispensing with an unnecessary check request.

Abstract: An information transfer apparatus for transferring memory operand data from a source address in a memory region to a destination address, including a first and second data overlap detecting circuits. If either detecting circuit indicates that data overlap is not present, the data transfer takes place word-by-word. In the case overlap is present, the data is transferred in bytes. The first detecting circuit checks for overlap by comparing the values and identities of predetermined bits in the source address and destination address. The second detecting circuit calculates the difference between the source and destination address and compares this difference to the length of the source operand data to be transferred.

Abstract: In an instruction prefetching device for use in a data processing system, a history table (26) serves not only as a branch history table for memorizing branch predictions but also as a page-over history table for memorizing page-over information. Even when a prefetch real instruction address coincides in an instruction address register 23 with one of page last real instruction addresses, the history table produces a table hit signal and a page-over real instruction address which corresponds to the prefetch real instruction address in the page-over information kept in the history table.

Abstract: An instruction prefetching device of a data processing system prefetches an instruction sequence, usually before decoding of a branch instruction being prefetched, by predicting a branch destination address which is preliminarily stored in a branch history table (46) and retrieved by an instruction address of the branch instruction. Preferably, a prediction evaluating circuit (66) evaluates the predicted destination address with attention directed to a result which is obtained by actually executing the branch instruction and indicates whether the branch instruction indicates "no go" or "go" to the branch. When the prediction is incorrect, the prefetch is suspended. Furthermore, the branch destination address is renewed to a new address obtained by decoding of the branch instruction. More preferably, a discriminator (73) discriminates whether or not the instruction being prefetched is really a branch instruction. If not, the predicted destination address is neglected.

Abstract: In a data processing system capable of processing instructions under pipeline control in a plurality of stages including an executing stage, an instruction prefetching device comprises a prediction checking circuit (66, 67) coupled to a predicting circuit (52, 53) and an instruction executing circuit (32, 33, 37, 38) and a prefetch controlling circuit (47, 86) coupled to the predicting circuit and the checking circuit. In one of the stages that is prior to the executing stage, the checking circuit checks whether or not a prediction for a branch destination is correct. If the prediction is correct, prefetch is continued according to the prediction. If the prediction is incorrect prediction, the prefetch is continued according to a correct prediction with the incorrect prediction corrected immediately after the executing stage.

Abstract: Instructions of a loop are repeatedly prefetched with a branch history table (46) made to store a predicted branch direction of "go" to branch for a branch count instruction of the loop. The loop is left without renewing the predicted branch direction when a prediction evaluating circuit (66) finds that the predicted branch direction is incorrect. Alternatively, the predicted branch direction is temporarily renewed to "no go" to branch during penultimate execution of the branch count instruction before leave of the loop and then renewed back to "go" to branch during ultimate execution of the branch count instruction on leaving the loop. It is possible in either event to again enter the loop at once. Only when there is no data for a branch count instruction, the predicted branch direction must be stored in the branch history table together with a predicted branch destination address for an instruction which stands foremost in the loop.

Abstract: The system includes a fetching circuit which sequentially fetches instructions to be executed. Certain of the instructions require that a predetermined condition code be present prior to being executed and certain of the instructions cause a condition code to be generated as a result of their execution. Condition code generators are provided for generating condition codes in response to execution of the instructions causing generation of condition codes. A circuit is also provided which is responsive to the sequentially fetched instructions for individually determining which of the instructions is to cause generation of a condition code, and which of the condition code generators is to generate a condition code for each of the determined instructions. The determined condition code generators are monitored, and a decision is made as to when a valid condition code has been generated by the monitored generator. A signal is produced when a valid condition code is generated.