Patents by Inventor Toshitsugu Ishii

Toshitsugu Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11860225
    Abstract: A test apparatus includes a test board, a unit, and a probe pin housed in the unit. First and second tip portions of the probe pin have the same shape as each other. A first external terminal of a first semiconductor package is brought into contact with the first tip portion of the probe pin and the second tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the first semiconductor package. Then, the unit is turned upside down and rearranged in the test apparatus. Thereafter, a second external terminal of a second semiconductor package is brought into contact with the second tip portion of the probe pin and the first tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the second semiconductor package.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: January 2, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Fukumi Unokuchi, Toshitsugu Ishii
  • Patent number: 11740259
    Abstract: An inspection terminal provided in a test device has a main body portion including a support portion that is curved; a plate-shaped portion integrally connected to the support portion and extending in a first direction; a tip portion integrally connected to the plate-shaped portion and having a larger dimension in a second direction intersecting with the first direction than that of the plate-shaped portion in the second direction; and a slit formed from the tip portion to the plate-shaped portion so as not to reach the support portion of the inspection terminal. The tip portion of the inspection terminal has a first contact portion and a second contact portion that are separated from each other by way of via the slit, and each contact portion is brought into contact with an external terminal of a semiconductor package, and an electrical test of the semiconductor package is performed.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: August 29, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshitsugu Ishii
  • Publication number: 20230266386
    Abstract: A test apparatus includes a test board, a unit, and a probe pin housed in the unit. First and second tip portions of the probe pin have the same shape as each other. A first external terminal of a first semiconductor package is brought into contact with the first tip portion of the probe pin and the second tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the first semiconductor package. Then, the unit is turned upside down and rearranged in the test apparatus. Thereafter, a second external terminal of a second semiconductor package is brought into contact with the second tip portion of the probe pin and the first tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the second semiconductor package.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Inventors: Fukumi UNOKUCHI, Toshitsugu ISHII
  • Publication number: 20230266362
    Abstract: An inspection terminal provided in a test device has a main body portion including a support portion that is curved; a plate-shaped portion integrally connected to the support portion and extending in a first direction; a tip portion integrally connected to the plate-shaped portion and having a larger dimension in a second direction intersecting with the first direction than that of the plate-shaped portion in the second direction; and a slit formed from the tip portion to the plate-shaped portion so as not to reach the support portion of the inspection terminal. The tip portion of the inspection terminal has a first contact portion and a second contact portion that are separated from each other by way of via the slit, and each contact portion is brought into contact with an external terminal of a semiconductor package, and an electrical test of the semiconductor package is performed.
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Inventor: Toshitsugu ISHII
  • Patent number: 10551432
    Abstract: A semiconductor device is manufactured at an improved efficiency. The method of the invention includes a step of carrying out an electrical test by bringing an external terminal electrically coupled to a semiconductor chip mounted on a semiconductor device into contact with a tip portion of a probe pin coupled to a test circuit and thereby electrically coupling the semiconductor chip to the test circuit. The probe pin has a tip portion comprised of a base material, a nickel film formed thereon, and a conductive film formed thereon and made of silver. The conductive film is thicker than the nickel film.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Publication number: 20180340976
    Abstract: A semiconductor device is manufactured at an improved efficiency. The method of the invention includes a step of carrying out an electrical test by bringing an external terminal electrically coupled to a semiconductor chip mounted on a semiconductor device into contact with a tip portion of a probe pin coupled to a test circuit and thereby electrically coupling the semiconductor chip to the test circuit. The probe pin has a tip portion comprised of a base material, a nickel film formed thereon, and a conductive film formed thereon and made of silver. The conductive film is thicker than the nickel film.
    Type: Application
    Filed: April 17, 2018
    Publication date: November 29, 2018
    Inventors: Toshitsugu ISHII, Naohiro MAKIHIRA, Hidekazu IWASAKI, Jun MATSUHASHI
  • Patent number: 10109568
    Abstract: The present invention is directed to improve reliability of a semiconductor device. A semiconductor device manufacturing method includes: (a) a step of attaching a BGA having a solder ball to a socket for a burn-in test; and (b) a step of performing a burn-in test of the BGA by sandwiching the solder ball by conductive contact pins in the socket. The contact pin in the socket has a first projection part which is conductive and extends along an attachment direction of the BGA and a second projection part which is conductive, provided along a direction crossing the extension direction of the first projection part, and placed so as to face the surface on the attachment side of the BGA of the solder ball. In the step (b), a burn-in test of the BGA is performed in a state where the first projection parts in the contact pins are in contact with the solder ball.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: October 23, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Jun Matsuhashi, Naohiro Makihira, Hidekazu Iwasaki, Toshitsugu Ishii
  • Patent number: 9945903
    Abstract: This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Publication number: 20180102310
    Abstract: The present invention is directed to improve reliability of a semiconductor device. A semiconductor device manufacturing method includes: (a) a step of attaching a BGA having a solder ball to a socket for a burn-in test; and (b) a step of performing a burn-in test of the BGA by sandwiching the solder ball by conductive contact pins in the socket. The contact pin in the socket has a first projection part which is conductive and extends along an attachment direction of the BGA and a second projection part which is conductive, provided along a direction crossing the extension direction of the first projection part, and placed so as to face the surface on the attachment side of the BGA of the solder ball. In the step (b), a burn-in test of the BGA is performed in a state where the first projection parts in the contact pins are in contact with the solder ball.
    Type: Application
    Filed: August 10, 2017
    Publication date: April 12, 2018
    Inventors: Jun MATSUHASHI, Naohiro MAKIHIRA, Hidekazu IWASAKI, Toshitsugu ISHII
  • Patent number: 9905482
    Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: February 27, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Publication number: 20170338159
    Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.
    Type: Application
    Filed: August 9, 2017
    Publication date: November 23, 2017
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Patent number: 9761501
    Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: September 12, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Publication number: 20170025318
    Abstract: This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.
    Type: Application
    Filed: May 10, 2016
    Publication date: January 26, 2017
    Inventors: Toshitsugu ISHII, Naohiro MAKIHIRA, Hidekazu IWASAKI, Jun MATSUHASHI
  • Patent number: 9515000
    Abstract: The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins. Further, the first contact pin has a support portion extending in a y direction and a tip portion connected to the support portion. The second contact pin also has a support portion extending in the y direction and a tip portion connected to the support portion. Here, the support portion of the first contact pin and the support portion of the second contact pin are arranged side by side along an x direction in a horizontal plane (xy plane). Further, the tip portion of the second contact pin is shifted from the tip portion of the first contact pin along the y direction in the horizontal plane, crossing (perpendicular to) the x direction.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: December 6, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Publication number: 20160141215
    Abstract: The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins. Further, the first contact pin has a support portion extending in a y direction and a tip portion connected to the support portion. The second contact pin also has a support portion extending in the y direction and a tip portion connected to the support portion. Here, the support portion of the first contact pin and the support portion of the second contact pin are arranged side by side along an x direction in a horizontal plane (xy plane). Further, the tip portion of the second contact pin is shifted from the tip portion of the first contact pin along the y direction in the horizontal plane, crossing (perpendicular to) the x direction.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 19, 2016
    Inventors: Toshitsugu ISHII, Naohiro MAKIHIRA, Hidekazu IWASAKI, Jun MATSUHASHI
  • Publication number: 20160064291
    Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.
    Type: Application
    Filed: April 11, 2013
    Publication date: March 3, 2016
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Patent number: 5174793
    Abstract: A method of plant cultivaton and growth acceleration includes enclosing the plants within a reflective chamber, controlling the CO.sub.2 concentration within said chamber so as to be at least 200 ppm, and irradiating the plants substantially omnidirectionally with a light intensity of approximately 3000 lux, while stably regulating the ambient temperature, relative humidity and nutrient supply.
    Type: Grant
    Filed: December 23, 1988
    Date of Patent: December 29, 1992
    Assignee: Mitsubishi Denki K.K.
    Inventors: Akira Ikeda, Shigeki Nakayama, Kenji Ezaki, Toshitsugu Ishii
  • Patent number: 4985224
    Abstract: Silica powder or a mixture of silica powder and silicon nitride whisker is heated at a temperature ranging from 800.degree. C. to 1,700.degree. C. in a gas mixture of ammonia gas (NH.sub.3) and hydrocarbon gas (C.sub.m H.sub.n) so as to produce silicon nitride whisker. The gas mixture flows at the rate of 10 mm/sec or less. The NH.sub.3 /CH.sub.4 ratio of the ammonia to the hydrocarbon, expressed as CH.sub.4, ranges from 0.5:1 to 2000:1 by volume. The silica powder is preferably mixed with at least one of six catalysts: transition metals; alkali metals; alkaline earth metals; halides of transition metals; halides of alkali metals; and alkaline earth metals. One mol part of the silica powder is mixed with 0.001-1.0 mol part of the catalyst.
    Type: Grant
    Filed: October 11, 1989
    Date of Patent: January 15, 1991
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Isao Imai, Toshitsugu Ishii, Kouichi Sueyoshi
  • Patent number: 4975260
    Abstract: Metal nitride powder is prepared by heating a mixture substantially containing powder of a metal oxide or a metal hydroxide in a mixed gas of ammonia gas (NH.sub.3) and a hydrocarbon gas (CmHn) at a temperature ranging from 1300.degree. C. to 1,600.degree. C., in which the mixed gas has a ratio of ammonia gas (NH.sub.3) to hydrocarbon gas (CmHn) translated into CH.sub.4, ranging from 10 (NH.sub.3) to 1.0 (CH.sub.4) to 2,000 (NH.sub.3) to 1 (CH.sub.4), by volume.The metal nitride powder contains lesser amounts of oxygen and carbon.
    Type: Grant
    Filed: April 5, 1989
    Date of Patent: December 4, 1990
    Assignee: Toshiba Ceramics Co., Ltd.
    Inventors: Isao Imai, Toshitsugu Ishii, Kouichi Sueyoshi, Toshiyuki Hirao
  • Patent number: 4817332
    Abstract: A method of plant cultivation and growth acceleration includes enclosing the plants within a reflective chamber, controlling the CO.sub.2 concentration within said chamber so as to be at least 200 ppm, and irradiating the plants substantially omnidirectionally with a light intensity of approximately 3000 lux, while stably regulating the ambient temperature, relative humidity and nutrient supply.
    Type: Grant
    Filed: October 26, 1984
    Date of Patent: April 4, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Ikeda, Shigeki Nakayama, Kenji Ezaki, Toshitsugu Ishii, Isao Itakura