Patents by Inventor Toshitsugu Ishii
Toshitsugu Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11860225Abstract: A test apparatus includes a test board, a unit, and a probe pin housed in the unit. First and second tip portions of the probe pin have the same shape as each other. A first external terminal of a first semiconductor package is brought into contact with the first tip portion of the probe pin and the second tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the first semiconductor package. Then, the unit is turned upside down and rearranged in the test apparatus. Thereafter, a second external terminal of a second semiconductor package is brought into contact with the second tip portion of the probe pin and the first tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the second semiconductor package.Type: GrantFiled: February 23, 2022Date of Patent: January 2, 2024Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Fukumi Unokuchi, Toshitsugu Ishii
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Patent number: 11740259Abstract: An inspection terminal provided in a test device has a main body portion including a support portion that is curved; a plate-shaped portion integrally connected to the support portion and extending in a first direction; a tip portion integrally connected to the plate-shaped portion and having a larger dimension in a second direction intersecting with the first direction than that of the plate-shaped portion in the second direction; and a slit formed from the tip portion to the plate-shaped portion so as not to reach the support portion of the inspection terminal. The tip portion of the inspection terminal has a first contact portion and a second contact portion that are separated from each other by way of via the slit, and each contact portion is brought into contact with an external terminal of a semiconductor package, and an electrical test of the semiconductor package is performed.Type: GrantFiled: February 24, 2022Date of Patent: August 29, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Toshitsugu Ishii
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Publication number: 20230266386Abstract: A test apparatus includes a test board, a unit, and a probe pin housed in the unit. First and second tip portions of the probe pin have the same shape as each other. A first external terminal of a first semiconductor package is brought into contact with the first tip portion of the probe pin and the second tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the first semiconductor package. Then, the unit is turned upside down and rearranged in the test apparatus. Thereafter, a second external terminal of a second semiconductor package is brought into contact with the second tip portion of the probe pin and the first tip portion thereof is brought into contact with the terminal of the test board, thereby performing an electrical test of the second semiconductor package.Type: ApplicationFiled: February 23, 2022Publication date: August 24, 2023Inventors: Fukumi UNOKUCHI, Toshitsugu ISHII
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Publication number: 20230266362Abstract: An inspection terminal provided in a test device has a main body portion including a support portion that is curved; a plate-shaped portion integrally connected to the support portion and extending in a first direction; a tip portion integrally connected to the plate-shaped portion and having a larger dimension in a second direction intersecting with the first direction than that of the plate-shaped portion in the second direction; and a slit formed from the tip portion to the plate-shaped portion so as not to reach the support portion of the inspection terminal. The tip portion of the inspection terminal has a first contact portion and a second contact portion that are separated from each other by way of via the slit, and each contact portion is brought into contact with an external terminal of a semiconductor package, and an electrical test of the semiconductor package is performed.Type: ApplicationFiled: February 24, 2022Publication date: August 24, 2023Inventor: Toshitsugu ISHII
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Patent number: 10551432Abstract: A semiconductor device is manufactured at an improved efficiency. The method of the invention includes a step of carrying out an electrical test by bringing an external terminal electrically coupled to a semiconductor chip mounted on a semiconductor device into contact with a tip portion of a probe pin coupled to a test circuit and thereby electrically coupling the semiconductor chip to the test circuit. The probe pin has a tip portion comprised of a base material, a nickel film formed thereon, and a conductive film formed thereon and made of silver. The conductive film is thicker than the nickel film.Type: GrantFiled: April 17, 2018Date of Patent: February 4, 2020Assignee: Renesas Electronics CorporationInventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Publication number: 20180340976Abstract: A semiconductor device is manufactured at an improved efficiency. The method of the invention includes a step of carrying out an electrical test by bringing an external terminal electrically coupled to a semiconductor chip mounted on a semiconductor device into contact with a tip portion of a probe pin coupled to a test circuit and thereby electrically coupling the semiconductor chip to the test circuit. The probe pin has a tip portion comprised of a base material, a nickel film formed thereon, and a conductive film formed thereon and made of silver. The conductive film is thicker than the nickel film.Type: ApplicationFiled: April 17, 2018Publication date: November 29, 2018Inventors: Toshitsugu ISHII, Naohiro MAKIHIRA, Hidekazu IWASAKI, Jun MATSUHASHI
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Patent number: 10109568Abstract: The present invention is directed to improve reliability of a semiconductor device. A semiconductor device manufacturing method includes: (a) a step of attaching a BGA having a solder ball to a socket for a burn-in test; and (b) a step of performing a burn-in test of the BGA by sandwiching the solder ball by conductive contact pins in the socket. The contact pin in the socket has a first projection part which is conductive and extends along an attachment direction of the BGA and a second projection part which is conductive, provided along a direction crossing the extension direction of the first projection part, and placed so as to face the surface on the attachment side of the BGA of the solder ball. In the step (b), a burn-in test of the BGA is performed in a state where the first projection parts in the contact pins are in contact with the solder ball.Type: GrantFiled: August 10, 2017Date of Patent: October 23, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Jun Matsuhashi, Naohiro Makihira, Hidekazu Iwasaki, Toshitsugu Ishii
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Patent number: 9945903Abstract: This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.Type: GrantFiled: May 10, 2016Date of Patent: April 17, 2018Assignee: Renesas Electronics CorporationInventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Publication number: 20180102310Abstract: The present invention is directed to improve reliability of a semiconductor device. A semiconductor device manufacturing method includes: (a) a step of attaching a BGA having a solder ball to a socket for a burn-in test; and (b) a step of performing a burn-in test of the BGA by sandwiching the solder ball by conductive contact pins in the socket. The contact pin in the socket has a first projection part which is conductive and extends along an attachment direction of the BGA and a second projection part which is conductive, provided along a direction crossing the extension direction of the first projection part, and placed so as to face the surface on the attachment side of the BGA of the solder ball. In the step (b), a burn-in test of the BGA is performed in a state where the first projection parts in the contact pins are in contact with the solder ball.Type: ApplicationFiled: August 10, 2017Publication date: April 12, 2018Inventors: Jun MATSUHASHI, Naohiro MAKIHIRA, Hidekazu IWASAKI, Toshitsugu ISHII
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Patent number: 9905482Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.Type: GrantFiled: August 9, 2017Date of Patent: February 27, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Publication number: 20170338159Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.Type: ApplicationFiled: August 9, 2017Publication date: November 23, 2017Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Patent number: 9761501Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.Type: GrantFiled: April 11, 2013Date of Patent: September 12, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Publication number: 20170025318Abstract: This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.Type: ApplicationFiled: May 10, 2016Publication date: January 26, 2017Inventors: Toshitsugu ISHII, Naohiro MAKIHIRA, Hidekazu IWASAKI, Jun MATSUHASHI
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Patent number: 9515000Abstract: The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins. Further, the first contact pin has a support portion extending in a y direction and a tip portion connected to the support portion. The second contact pin also has a support portion extending in the y direction and a tip portion connected to the support portion. Here, the support portion of the first contact pin and the support portion of the second contact pin are arranged side by side along an x direction in a horizontal plane (xy plane). Further, the tip portion of the second contact pin is shifted from the tip portion of the first contact pin along the y direction in the horizontal plane, crossing (perpendicular to) the x direction.Type: GrantFiled: October 30, 2015Date of Patent: December 6, 2016Assignee: Renesas Electronics CorporationInventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Publication number: 20160141215Abstract: The reliability of multipoint contact by a contact pin with an external terminal is improved while achieving an improvement in easiness of manufacture of the contact pin. The contact pin includes first and second contact pins. Further, the first contact pin has a support portion extending in a y direction and a tip portion connected to the support portion. The second contact pin also has a support portion extending in the y direction and a tip portion connected to the support portion. Here, the support portion of the first contact pin and the support portion of the second contact pin are arranged side by side along an x direction in a horizontal plane (xy plane). Further, the tip portion of the second contact pin is shifted from the tip portion of the first contact pin along the y direction in the horizontal plane, crossing (perpendicular to) the x direction.Type: ApplicationFiled: October 30, 2015Publication date: May 19, 2016Inventors: Toshitsugu ISHII, Naohiro MAKIHIRA, Hidekazu IWASAKI, Jun MATSUHASHI
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Publication number: 20160064291Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.Type: ApplicationFiled: April 11, 2013Publication date: March 3, 2016Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
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Patent number: 5174793Abstract: A method of plant cultivaton and growth acceleration includes enclosing the plants within a reflective chamber, controlling the CO.sub.2 concentration within said chamber so as to be at least 200 ppm, and irradiating the plants substantially omnidirectionally with a light intensity of approximately 3000 lux, while stably regulating the ambient temperature, relative humidity and nutrient supply.Type: GrantFiled: December 23, 1988Date of Patent: December 29, 1992Assignee: Mitsubishi Denki K.K.Inventors: Akira Ikeda, Shigeki Nakayama, Kenji Ezaki, Toshitsugu Ishii
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Patent number: 4985224Abstract: Silica powder or a mixture of silica powder and silicon nitride whisker is heated at a temperature ranging from 800.degree. C. to 1,700.degree. C. in a gas mixture of ammonia gas (NH.sub.3) and hydrocarbon gas (C.sub.m H.sub.n) so as to produce silicon nitride whisker. The gas mixture flows at the rate of 10 mm/sec or less. The NH.sub.3 /CH.sub.4 ratio of the ammonia to the hydrocarbon, expressed as CH.sub.4, ranges from 0.5:1 to 2000:1 by volume. The silica powder is preferably mixed with at least one of six catalysts: transition metals; alkali metals; alkaline earth metals; halides of transition metals; halides of alkali metals; and alkaline earth metals. One mol part of the silica powder is mixed with 0.001-1.0 mol part of the catalyst.Type: GrantFiled: October 11, 1989Date of Patent: January 15, 1991Assignee: Toshiba Ceramics Co., Ltd.Inventors: Isao Imai, Toshitsugu Ishii, Kouichi Sueyoshi
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Patent number: 4975260Abstract: Metal nitride powder is prepared by heating a mixture substantially containing powder of a metal oxide or a metal hydroxide in a mixed gas of ammonia gas (NH.sub.3) and a hydrocarbon gas (CmHn) at a temperature ranging from 1300.degree. C. to 1,600.degree. C., in which the mixed gas has a ratio of ammonia gas (NH.sub.3) to hydrocarbon gas (CmHn) translated into CH.sub.4, ranging from 10 (NH.sub.3) to 1.0 (CH.sub.4) to 2,000 (NH.sub.3) to 1 (CH.sub.4), by volume.The metal nitride powder contains lesser amounts of oxygen and carbon.Type: GrantFiled: April 5, 1989Date of Patent: December 4, 1990Assignee: Toshiba Ceramics Co., Ltd.Inventors: Isao Imai, Toshitsugu Ishii, Kouichi Sueyoshi, Toshiyuki Hirao
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Patent number: 4817332Abstract: A method of plant cultivation and growth acceleration includes enclosing the plants within a reflective chamber, controlling the CO.sub.2 concentration within said chamber so as to be at least 200 ppm, and irradiating the plants substantially omnidirectionally with a light intensity of approximately 3000 lux, while stably regulating the ambient temperature, relative humidity and nutrient supply.Type: GrantFiled: October 26, 1984Date of Patent: April 4, 1989Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akira Ikeda, Shigeki Nakayama, Kenji Ezaki, Toshitsugu Ishii, Isao Itakura