Abstract: An electronic device may include a digital to analog converter receiving digital signals and outputting analog signals based on the received digital signals. The electronic device may also include a power source to supply current to the digital to analog converter. The digital to analog converter may include a first resistor ladder section to electrically couple an output node of the digital to analog converter to the power source via a first number of resistors in series. The digital to analog converter may also include a second resistor ladder section to electrically couple the output node to a reference voltage via a second number of resistors in series. The sum of the first number of resistors in series and the second number of resistors in series may be the same for each of the different analog signals.

Abstract: An electronic device may include a digital to analog converter receiving digital signals and outputting analog signals based on the received digital signals. The electronic device may also include a power source to supply current to the digital to analog converter. The digital to analog converter may include a first resistor ladder section to electrically couple an output node of the digital to analog converter to the power source via a first number of resistors in series. The digital to analog converter may also include a second resistor ladder section to electrically couple the output node to a reference voltage via a second number of resistors in series. The sum of the first number of resistors in series and the second number of resistors in series may be the same for each of the different analog signals.

Abstract: Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.

Abstract: A PLL circuit according to an exemplary aspect of the present invention includes: a PFD that detects a phase difference between two clock signals; an LPF that outputs a voltage based on a detection result of the PFD; a VCO that controls a frequency of a VCO output clock output based on the voltage; a frequency divider that divides a frequency of the VCO output clock and outputs an output clock; and an automatic adjustment circuit that adjusts a frequency division ratio of the frequency divider based on the voltage. The automatic adjustment circuit includes a comparison circuit that outputs a control signal for controlling the frequency divider and a control signal for controlling the reference voltage. This circuit configuration makes it possible to control an oscillation frequency of a PLL circuit with accuracy and stability.

Abstract: A PLL circuit according to an exemplary aspect of the present invention includes: a PFD that detects a phase difference between two clock signals; an LPF that outputs a voltage based on a detection result of the PFD; a VCO that controls a frequency of a VCO output clock output based on the voltage; a frequency divider that divides a frequency of the VCO output clock and outputs an output clock; and an automatic adjustment circuit that adjusts a frequency division ratio of the frequency divider based on the voltage. The automatic adjustment circuit includes a comparison circuit that outputs a control signal for controlling the frequency divider and a control signal for controlling the reference voltage. This circuit configuration makes it possible to control an oscillation frequency of a PLL circuit with accuracy and stability.

Abstract: Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error.

Abstract: A demultiplexer circuit includes a first serial-to-parallel conversion circuit for receiving input serial data and for performing serial-to-parallel conversion to output resultant data to parallel paths, a code detection circuit for activating and outputting a detection signal on detection of coincidence between output data sent out from the first serial-to-parallel conversion circuit to the parallel paths and a predetermined check code, a circuit for generating recovery clocks of a period corresponding to the length of a predetermined number of bits of the input serial data, and for varying the period of the recovery clocks, in case the detection signal from the code detection circuit is activated, in dependence upon bit deviation of the detection signal, to output resulting recovery clocks; and a second serial-to-parallel conversion circuit for converting data serially transmitted on the parallel paths into parallel data to output resulting parallel data responsive to the recovery clocks.

Abstract: Demultiplexer capable of coping with bit deviation of a comma code to suppress increase of operating frequency. The demultiplexer comprises a circuit (20) serially supplied with received data to perform serial-to-parallel conversion on the received data, a comma detection circuit (30) for activating a comma detection signal on detection of coincidence between the serial data transferred on parallel paths with clocks corresponding to received clocks halved in frequency and a comma code, and a control circuit (137-139, 40) for elongating and outputting the activated time duration of the comma detection signal by a predetermined time. The demultiplexer also includes a recovery clock generating circuit (50) composed of a state machine transferred between different states based on the frequency-halved clocks and which, on receipt of an output signal of a control circuit (40), varies the period of the recovery clock to output the resulting clock.