Patents by Inventor Toshiya Akamatsu
Toshiya Akamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10062658Abstract: A surface of at least one of a connection terminal of an electronic component and a connection terminal of a circuit board is covered with a protection layer made of a AgSn alloy. The connection terminal of the electronic component is soldered to the connection terminal of the circuit board.Type: GrantFiled: July 6, 2015Date of Patent: August 28, 2018Assignee: FUJITSU LIMITEDInventors: Seiki Sakuyama, Toshiya Akamatsu, Nobuhiro Imaizumi, Keisuke Uenishi, Kenichi Yasaka, Toru Sakai
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Patent number: 10056342Abstract: A surface of at least one of a connection terminal of an electronic component and a connection terminal of a circuit board is covered with a protection layer made of a AgSn alloy. The connection terminal of the electronic component is soldered to the connection terminal of the circuit board.Type: GrantFiled: October 31, 2012Date of Patent: August 21, 2018Assignee: FUJITSU LIMITEDInventors: Seiki Sakuyama, Toshiya Akamatsu, Nobuhiro Imaizumi, Keisuke Uenishi, Kenichi Yasaka, Toru Sakai
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Publication number: 20170250153Abstract: An electronic part includes a substrate, an insulating film formed over the substrate, a first pillar electrode, a first solder formed over the first pillar electrode, a second pillar electrode, and a second solder formed over the second pillar electrode. The first pillar electrode over which the first solder is formed is formed over a first region of an insulating film including a level difference between a first opening portion and a peripheral portion of the first opening portion. The second pillar electrode over which the second solder is formed is formed over a second region of the insulating film including a second opening portion whose opening area is larger than that of the first opening portion. For example, the second pillar electrode over which the second solder is formed is formed over the second opening portion of the insulating film.Type: ApplicationFiled: January 3, 2017Publication date: August 31, 2017Applicant: FUJITSU LIMITEDInventors: Ryo Kikuchi, TOSHIYA AKAMATSU
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Patent number: 9472527Abstract: Surfaces of a semiconductor chip and a circuit board are made to face each other, and upper portions of stoppers of the circuit board are fit into regions between adjacent stoppers of rail grooves of the semiconductor chip, and upper portions of the stoppers of the semiconductor chip are fit into regions between the adjacent stoppers of rail grooves of the circuit board, whereby side surfaces of first terminals of the semiconductor chip and side surfaces of second terminals of the circuit board are electrically connected.Type: GrantFiled: January 5, 2015Date of Patent: October 18, 2016Assignee: FUJITSU LIMITEDInventors: Toshiya Akamatsu, Muneyuki Odaira
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Patent number: 9412715Abstract: A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on which a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.Type: GrantFiled: October 7, 2014Date of Patent: August 9, 2016Assignee: FUJITSU LIMITEDInventors: Kozo Shimizu, Seiki Sakuyama, Toshiya Akamatsu
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Patent number: 9235001Abstract: An optical device includes: an optical integrated circuit chip that comprises an optical integrated circuit and an optical interface connected thereto; an electronic circuit chip that comprises an electronic circuit connected to the optical integrated circuit; a through wiring board that comprises a through wiring connected to the electronic circuit chip; a first bump that connects the optical integrated circuit and the electronic circuit between the optical integrated circuit chip and the electronic circuit chip; a second bump that connects the electronic circuit and the through wiring between the electronic circuit chip and the through wiring board; and a third bump connected to an end portion on an opposite side to the second bump of the through wiring. The optical integrated circuit chip and the through wiring board are disposed on a side of a first main surface of the electronic circuit chip.Type: GrantFiled: April 15, 2015Date of Patent: January 12, 2016Assignee: FUJITSU LIMITEDInventors: Shigeaki Sekiguchi, Nobuhiro Imaizumi, Toshiya Akamatsu, Shinji Tadaki, Akinori Hayakawa
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Publication number: 20150371962Abstract: A terminal structure includes: a pillar containing a first metal material; and a cover layer covering an upper surface and a side surface of the pillar, the cover layer containing a second metal material into which a solder material diffuses more slowly than into the first metal material. And the terminal structure further includes a bonding layer over the cover layer, the bonding layer containing a metal material capable of solder bonding.Type: ApplicationFiled: June 9, 2015Publication date: December 24, 2015Applicant: FUJITSU LIMITEDInventor: TOSHIYA AKAMATSU
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Publication number: 20150323738Abstract: An optical device includes: an optical integrated circuit chip that comprises an optical integrated circuit and an optical interface connected thereto; an electronic circuit chip that comprises an electronic circuit connected to the optical integrated circuit; a through wiring board that comprises a through wiring connected to the electronic circuit chip; a first bump that connects the optical integrated circuit and the electronic circuit between the optical integrated circuit chip and the electronic circuit chip; a second bump that connects the electronic circuit and the through wiring between the electronic circuit chip and the through wiring board; and a third bump connected to an end portion on an opposite side to the second bump of the through wiring. The optical integrated circuit chip and the through wiring board are disposed on a side of a first main surface of the electronic circuit chip.Type: ApplicationFiled: April 15, 2015Publication date: November 12, 2015Inventors: Shigeaki Sekiguchi, Nobuhiro Imaizumi, Toshiya Akamatsu, Shinji Tadaki, Akinori Hayakawa
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Publication number: 20150311171Abstract: A surface of a connection terminal of an electronic component is covered with a protection layer made of a AgSn alloy. The electronic component is soldered to a connection terminal of a circuit board.Type: ApplicationFiled: July 6, 2015Publication date: October 29, 2015Applicant: FUJITSU LIMITEDInventors: Seiki SAKUYAMA, Toshiya Akamatsu, Nobuhiro Imaizumi, Keisuke Uenishi, Kenichi Yasaka, Toru Sakai
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Publication number: 20150221607Abstract: Surfaces of a semiconductor chip and a circuit board are made to face each other, and upper portions of stoppers of the circuit board are fit into regions between adjacent stoppers of rail grooves of the semiconductor chip, and upper portions of the stoppers of the semiconductor chip are fit into regions between the adjacent stoppers of rail grooves of the circuit board, whereby side surfaces of first terminals of the semiconductor chip and side surfaces of second terminals of the circuit board are electrically connected.Type: ApplicationFiled: January 5, 2015Publication date: August 6, 2015Inventors: TOSHIYA AKAMATSU, Muneyuki Odaira
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Patent number: 8952271Abstract: There is provided a circuit board to which a solder ball composed of a lead (Pb)-free solder is to be connected, a semiconductor device including an electrode and a solder ball composed of a lead (Pb)-free solder disposed on the electrode, and a method of manufacturing the semiconductor device, in which mounting reliability can be improved by enhancing the bonding strength (adhesion strength) between the solder ball composed of a lead (Pb)-free solder and the electrode.Type: GrantFiled: December 13, 2013Date of Patent: February 10, 2015Assignee: Fujitsu LimitedInventors: Masaharu Furuyama, Daisuke Mizutani, Seiki Sakuyama, Toshiya Akamatsu
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Publication number: 20150024555Abstract: A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on which a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.Type: ApplicationFiled: October 7, 2014Publication date: January 22, 2015Applicant: FUJITSU LIMITEDInventors: Kozo SHIMIZU, Seiki Sakuyama, Toshiya Akamatsu
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Patent number: 8901751Abstract: A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on which a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.Type: GrantFiled: October 1, 2012Date of Patent: December 2, 2014Assignee: Fujitsu LimitedInventors: Kozo Shimizu, Seiki Sakuyama, Toshiya Akamatsu
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Patent number: 8740047Abstract: A method of manufacturing an electronic apparatus including a first and a second components, includes: forming a first solder bump on one of the first component and the second component; forming a second solder bump on the other one of the first component and the second component; bringing the first solder bump into contact with the second solder bump at a temperature higher than the liquidus temperature of any of the first and the second solder bumps such that the first and the second solder bumps are fused together to form a solder joint of an alloy having a lower liquidus temperature than any of the first and the second solder bumps; and solidifying the solder joint between the first and the second component.Type: GrantFiled: September 11, 2013Date of Patent: June 3, 2014Assignee: Fujitsu LimitedInventors: Seiki Sakuyama, Toshiya Akamatsu, Masateru Koide
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Publication number: 20140103097Abstract: There is provided a circuit board to which a solder ball composed of a lead (Pb)-free solder is to be connected, a semiconductor device including an electrode and a solder ball composed of a lead (Pb)-free solder disposed on the electrode, and a method of manufacturing the semiconductor device, in which mounting reliability can be improved by enhancing the bonding strength (adhesion strength) between the solder ball composed of a lead (Pb)-free solder and the electrode.Type: ApplicationFiled: December 13, 2013Publication date: April 17, 2014Applicant: FUJITSU LIMITEDInventors: Masaharu Furuyama, Daisuke Mizutani, Seiki Sakuyama, Toshiya Akamatsu
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Patent number: 8692386Abstract: A semiconductor device includes a semiconductor element and an electronic element. The semiconductor element has a first protruding electrode, and the electronic element has a second protruding electrode. A substrate is disposed between the semiconductor element and the electronic element. The substrate has a through-hole in which the first and second protruding electrodes are fitted. The first and second protruding electrodes are connected together inside the through-hole of the substrate.Type: GrantFiled: December 15, 2011Date of Patent: April 8, 2014Assignee: Fujitsu LimitedInventor: Toshiya Akamatsu
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Patent number: 8673762Abstract: A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.Type: GrantFiled: December 7, 2011Date of Patent: March 18, 2014Assignee: Fujitsu LimitedInventors: Toshiya Akamatsu, Nobuhiro Imaizumi, Seiki Sakuyama, Keisuke Uenishi, Tetsuhiro Nakanishi
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Publication number: 20140008114Abstract: A method of manufacturing an electronic apparatus including a first and a second components, includes: forming a first solder bump on one of the first component and the second component; forming a second solder bump on the other one of the first component and the second component; bringing the first solder bump into contact with the second solder bump at a temperature higher than the liquidus temperature of any of the first and the second solder bumps such that the first and the second solder bumps are fused together to form a solder joint of an alloy having a lower liquidus temperature than any of the first and the second solder bumps; and solidifying the solder joint between the first and the second component.Type: ApplicationFiled: September 11, 2013Publication date: January 9, 2014Applicant: FUJITSU LIMITEDInventors: Seiki Sakuyama, Toshiya Akamatsu, Masateru Koide
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Patent number: 8556157Abstract: A method of manufacturing an electronic apparatus including a first and a second components, includes: forming a first solder bump on one of the first component and the second component; forming a second solder bump on the other one of the first component and the second component; bringing the first solder bump into contact with the second solder bump at a temperature higher than the liquidus temperature of any of the first and the second solder bumps such that the first and the second solder bumps are fused together to form a solder joint of an alloy having a lower liquidus temperature than any of the first and the second solder bumps; and solidifying the solder joint between the first and the second component.Type: GrantFiled: May 23, 2011Date of Patent: October 15, 2013Assignee: Fujitsu LimitedInventors: Seiki Sakuyama, Toshiya Akamatsu, Masateru Koide
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Publication number: 20120193800Abstract: A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.Type: ApplicationFiled: December 7, 2011Publication date: August 2, 2012Applicant: FUJITSU LIMITEDInventors: Toshiya Akamatsu, Nobuhiro Imaizumi, Seiki Sakuyama, Keisuke Uenishi, Tetsuhiro Nakanishi