Patents by Inventor Toshiya Kato

Toshiya Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5355331
    Abstract: According to this invention, there is disclosed a semiconductor device in which a memory section and a logic section are arranged on the same semiconductor chip, comprising a high-resistance element constituting a memory cell, a low-resistance line connected to the high-resistance element, a power source line serving as a power source path from a power source pad, a switching element arranged between the low-resistance line and the power source line, and a control circuit for controlling the switching element.
    Type: Grant
    Filed: January 24, 1994
    Date of Patent: October 11, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinsuke Takase, Toshiya Kato
  • Patent number: 4970572
    Abstract: A semiconductor integrated circuit device of multi-layer interconnection structure includes a pad formed of a multilayer interconnection layer. The power source pad is connected to a power source interconnection layer via a lead-out interconnection layer which is formed of the same multilayer interconnection layer as that used to form the power source pad.
    Type: Grant
    Filed: March 3, 1989
    Date of Patent: November 13, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kato, Motohiro Enkaku
  • Patent number: 4924290
    Abstract: A semiconductor device includes a circuit block formed on a semiconductor chip with multilayered wiring layers having two or more layers, and having a specific function assigned thereto, a first current path pattern formed in a first layer of the multilayered wiring layers and running around the circuit block, a second current path pattern formed in a second layer of the multilayered wiring layers and running around the circuit block, part of the second current path pattern lying over the first current path pattern and the other portion of the second current path pattern lying off the first current path pattern so as to define a connection space with a predetermined width between the first current path pattern and the second current path pattern, a first signal path pattern formed in the first layer of the multilayered wiring layers and serving as a signal path to the circuit block, a second signal path pattern formed in the second layer of the multilayered wiring layers and serving as the signal path to the
    Type: Grant
    Filed: August 30, 1988
    Date of Patent: May 8, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Motohiro Enkaku, Toshiya Kato
  • Patent number: 3933558
    Abstract: A laminated decorative sheet is prepared by applying a coating layer consisting of a thermo-setting resin composition on a base paper for a decorative laminate which has been prepared by incorporating a composition the whole or a major part of which is composed of a synthetic rubber and/or a thermo-plastic synthetic resin substance into the base paper during the paper making thereof or by impregnating the base paper with the thermo-plastic synthetic resin composition or with the mixture thereof; or alternatively is prepared by laminating another base paper for a decorative laminate which has been impregnated with the thermosetting resin composition on the above mentioned base paper containing the thermo-plastic synthetic resin composition, and the thus prepared layers are laminated under heat and pressure to form a laminated decorative sheet having smooth surface which is subjected to emboss-processing under a heating condition of at least 100.degree.
    Type: Grant
    Filed: May 25, 1973
    Date of Patent: January 20, 1976
    Assignees: Kohjin Co., Ltd., Aika Kogyo Co., Ltd.
    Inventors: Yasushi Takahata, Akira Karimori, Toshiya Kato, Katsuo Nomura