Abstract: A semiconductor integrated circuit (100) fetches read data from DDR-SDRAMs (110, 120) each operating in synchronization with a clock, and transfers the read data. The semiconductor integrated circuit (100) includes read buffers (104, 105) for fetching the read data from the DDR-SDRAMs (110, 120), and transferring the read data, latch timing control circuits (102, 103) for controlling respective latch timings with which the read buffers (104, 105) fetch the read data from the DDR-SDRAMs (110, 120) based on respective data strobe signals from the DDR-SDRAMs (110, 120), and a read timing control circuit (106) for controlling respective read timings with which the read buffers (104, 105) transfer the read data based on the latch timings of the latch timing control circuits (102, 103).

Abstract: A solid-state image sensing apparatus including a solid-state image sensing device and a signal processing circuit. The solid-state image sensing device includes: a vertical transfer unit, composed of transfer columns corresponding to columns of the light-to-electric conversion elements, operable to transfer, in a vertical direction, signal charges read out from the light-to-electric conversion elements; a horizontal transfer unit operable to receive the signal charges from the vertical transfer unit and transfer them in a horizontal direction. The signal processing circuit converts the signal charges from the horizontal transfer unit into pixel data, and rearranges it into a two-dimensional array. In the rearrangement, the signal processing circuit, per transfer of one piece of pixel data, cyclically selects a line memory out of three line memories, writes a piece of pixel data into the selected line memory, or reads a row of pixel data from the selected line memory.

Abstract: An interface circuit is provided for use in a semiconductor device which transmits and receives a signal to and from the outside. The interface circuit includes a signal input/output terminal for receiving a signal from the outside in a signal input mode and a signal from the semiconductor device in a signal output mode, an input buffer gate circuit having an input terminal connected to the signal input/output terminal and for outputting a signal received at the input terminal to the semiconductor device, and an input level control circuit for fixing a potential level at the input terminal of the input buffer gate circuit to a predetermined level in a signal no-supply mode and removing the fixation of the potential level in the signal output mode and in the signal input mode.

Abstract: A charge transfer implemented by a transfer section for transferring charges stored in image sensor elements along one direction on a surface where the image sensor elements are disposed is halted for a predetermined length of time. The charges are transferred from the transfer section without reading the charges from the image sensor elements after the charge transfer is halted for the predetermined length of time. A position where a defect is generated in an image pickup sensor is identified based on signal levels of the transferred charges. A defective signal level of the image pickup sensor generated on a line including the defect-generating position and in parallel with the one direction is corrected. As a result of the foregoing process, a display failure is precisely corrected.

Abstract: A semiconductor integrated circuit (100) fetches read data from DDR-SDRAMs (110, 120) each operating in synchronization with a clock, and transfers the read data. The semiconductor integrated circuit (100) includes read buffers (104, 105) for fetching the read data from the DDR-SDRAMs (110, 120), and transferring the read data, latch timing control circuits (102, 103) for controlling respective latch timings with which the read buffers (104, 105) fetch the read data from the DDR-SDRAMs (110, 120) based on respective data strobe signals from the DDR-SDRAMs (110, 120), and a read timing control circuit (106) for controlling respective read timings with which the read buffers (104, 105) transfer the read data based on the latch timings of the latch timing control circuits (102, 103).

Abstract: An interface circuit is provided for use in a semiconductor device which transmits and receives a signal to and from the outside. The interface circuit includes a signal input/output terminal for receiving a signal from the outside in a signal input mode and a signal from the semiconductor device in a signal output mode, an input buffer gate circuit having an input terminal connected to the signal input/output terminal and for outputting a signal received at the input terminal to the semiconductor device, and an input level control circuit for fixing a potential level at the input terminal of the input buffer gate circuit to a predetermined level in a signal no-supply mode and removing the fixation of the potential level in the signal output mode and in the signal input mode.

Abstract: A focus adjusting method for focusing a focus of a digital camera comprises an image signal converting step in which an imaging light entering an optical lens mechanism is converted into an image signal, an extracting step in which a high-frequency component of the image signal is selectively extracted, a signal generating step in which a luminance signal and a color difference signal are generated from the high-frequency component of the image signal selectively extracted, and a focus adjusting step in which a focusing position of the optical lens mechanism is adjusted using a high-frequency component of the luminance signal. According to the foregoing constitution, a focus adjustment can be realized with a high accuracy and at a high speed.

Abstract: An image processing device according to the present invention comprises an image signal operation unit, a correction data operation unit and a correcting unit. The image signal operation unit adjusts a white balance of an image signal by controlling a gain of the image signal for each color constituting the image signal. The correction data operation unit creates correction data for correcting an output of the image signal operation unit. The correcting unit further corrects the output of the image signal operation unit based on the correction data created by the correction data operation unit. According to the present invention, the white balance can be appropriately adjusted without losing subtle shades and shadows of a photographic object even in the case of an image signal including a noise level of a dark current.

Abstract: A charge transfer implemented by a transfer section for transferring charges stored in image sensor elements along one direction on a surface where the image sensor elements are disposed is halted for a predetermined length of time. The charges are transferred from the transfer section without reading the charges from the image sensor elements after the charge transfer is halted for the predetermined length of time. A position where a defect is generated in an image pickup sensor is identified based on signal levels of the transferred charges. A defective signal level of the image pickup sensor generated on a line including the defect-generating position and in parallel with the one direction is corrected. As a result of the foregoing process, a display failure is precisely corrected.

Abstract: A solid-state image sensing apparatus including a solid-state image sensing device and a signal processing circuit. The solid-state image sensing device includes: a vertical transfer unit, composed of transfer columns corresponding to columns of the light-to-electric conversion elements, operable to transfer, in a vertical direction, signal charges read out from the light-to-electric conversion elements; a horizontal transfer unit operable to receive the signal charges from the vertical transfer unit and transfer them in a horizontal direction. The signal processing circuit converts the signal charges from the horizontal transfer unit into pixel data, and rearranges it into a two-dimensional array. In the rearrangement, the signal processing circuit, per transfer of one piece of pixel data, cyclically selects a line memory out of three line memories, writes a piece of pixel data into the selected line memory, or reads a row of pixel data from the selected line memory.