Abstract: A PLL circuit according avoids any large change in a frequency in a VCO (5) even if an input horizontal synchronization signal suddenly changes or a level of the frequency decreases to a predetermined value or less, or disappears. The PLL circuit comprises a switch (3) to be provided on an output side of a phase comparator (2) to control an output voltage of the VCO by connecting to an AFC filter (4) and supplying a phase difference current according to a phase difference, during the time the horizontal synchronization signal is supplied. The comparator (2) compares a phase of an Hin signal through a delay circuit (1) with a phase of a return (RET) signal through a dividing circuit (6) and a delay circuit (7) from the VCO. With this structure, the comparator does not supply any phase difference current and does not make the VCO change at the time when the Hin signal is disappeared.

Abstract: In a data control system according to the present invention, a data storage unit such as a memory or a register of each slave apparatus receives supply of power from a first power source which supplies power to a master apparatus, and is separated from a second power source which supplies power to different circuits of the slave apparatus except the data storage section. A CPU of the master apparatus has a function of discriminating operation conditions of the two first and second power sources and controlling initialization of the slave apparatus including the data storage units and the other circuits. Each of the slave apparatus includes a first power-on reset circuit for detecting power-on of the first power source and outputting an initialization reset signal for the data storage unit, and a second power-on reset circuit for detecting power-on of the second power source and outputting an initialization reset signal of the circuits other than the data storage unit.

Abstract: An FM demodulator formed on a semiconductor chip generates a demodulated audio-frequency signal from an audio intermediate frequency signal through a phase locked loop constituted by a multiplier, a low-pass filter and a voltage-controlled oscillator. A variation of amplitude of the demodulated audio-frequency signal due to a temperature variation is compensated by a temperature compensating amplifier and a de-emphasis filter through first and second reference currents flowing out therefrom through an internal resistor fabricated on the same semiconductor chip and an external resistor.

Abstract: A pilot signal detection circuit comprises: a PLL circuit for generating a reference signal whose frequency is same as and phase-synchronized with a carrier of a pilot signal extracted from broadcasting waves; a sync-detector for sync-detecting the carrier by using the reference signal; a frequency signal generator for generating a first pair of signals having a frequency assigned to sound multiplex broadcasting and a phase difference of 90 degrees and a second pair of signals having a frequency assigned to stereophonic broadcasting and a phase difference of 90 degrees; multiplies for multiplying the signal output from the sync detector by the output signals from the frequency signal generator; squaring circuits for squaring the output signals from the multipliers; LPFs for filtering the output signals from the squaring circuits; an adder for adding the outputs of the LPFs, and a detector for detecting the pilot signal by comparing the output of the adder with a predetermined reference level.

Abstract: A pilot signal detection circuit receives a supply of a pilot signal produced by frequency-modulation of a predetermined third frequency carrier signal by a first discrimination signal of a first frequency and a second discrimination signal of a second frequency, and makes a discrimination between the first discrimination signal and the second discrimination signal by whether a signal detected is of the first frequency or of the second frequency. The pilot signal detection circuit is constituted by first and second multiplying and filtering stages. The first multiplying and filtering stage includes first and second multipliers and first and second low-pass filters. The first and second multipliers multiply the pilot signal respectively with the first reference signal and the second reference signal, and produce respectively first and second multiplied signals.

Abstract: A system for carrying out automatic fine tuning detection comprising a generating section for generating a video intermediate frequency signal from a radio wave, a filtering section connected to the generating section for filtering the video intermediate frequency signal supplied from the generating section, the filtering section having low and high frequency regions having different gains from each other, a subtracting section connected to both the generating section and filtering section for subtracting an output signal of the filtering section from the video intermediate frequency signal supplied by the generating section, an extracting section connected to the filtering section for fetching the output signal of the filtering section and subsequent extraction of a video carrier wave signal component from the output signal and a multiplying section connected to the subtracting section, the extracting section and the generating section for multiplying an output signal of the subtracting section by an output

Abstract: A filter circuit comprises a glass delay line for giving a predetermined amount of delay to an input signal, and an active filter connected to the glass delay line for performing an impedance matching for the glass delay line. By changing the transconductance g.sub.m of differential amplifiers which constitute the active filter, the amount of delay of the glass delay line can be adjusted.

Abstract: A multivoice signal switching circuit is incorporated in a circuit for demodulating a multivoice signal containing a main channel signal, a first subchannel signal, and a second subchannel signal, the latter two signals being treated for noise reduction. The demodulating circuit comprises a first circuit for extracting a main channel signal from the multivoice signal, a second circuit for extracting a first subchannel signal from the multivoice signal, and a third circuit for extracting a second subchannel signal. The above switching circuit receives the first and second subchannel signals and selectively outputs one of the two subchannel signals, to a decoder where the original signal is restored from the noise reduction treated signal. This signal is fed to an output circuit means together with the outputs of the first circuit, so that an audio signal is reproduced.