Patents by Inventor Toshiya Nakamori

Toshiya Nakamori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device
    Patent number: 9704801
    Abstract: A semiconductor memory device includes first and second stacked bodies and a conductive body. The first and second stacked bodies are disposed side by side on the conductive layer. The conductive body is provided between the first and second stacked bodies. The first and second stacked bodies each includes a plurality of electrode layers stacked on the conductive layer, a first insulating layer between adjacent electrode layers, a second insulating layer including a first portion and a second portion, and a semiconductor layer extending through the plurality of electrode layers. The first portion is provided between the first insulating layer and one of the adjacent electrode layers. The second portion is separated from the first portion and provided on an end surface of the first insulating layer facing the conductive body. The second insulating layer has a dielectric constant higher than a dielectric constant of the first insulating layer.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: July 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Sonehara, Masaru Kito, Toshiya Nakamori
  • Method of forming a semiconductor device introducing plural impurities to form plural wells
    Patent number: 8455338
    Abstract: A method for forming a semiconductor device includes the following processes. A first well including a memory cell region of a semiconductor substrate is formed. A second well including a first peripheral circuit region of the semiconductor substrate is formed after forming the first well.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: June 4, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Toshiya Nakamori
  • Method for manufacturing semiconductor device
    Patent number: 8173515
    Abstract: An oxide film and a liner film are formed on an inner wall of a trench in a semiconductor substrate. After filling an SOD film in the trench, a heat treatment is carried out. Part of the liner film in contact with the SOD film is removed to expose part of the SOD film. A heat treatment is carried out on the SOD film. An isolating region is formed by filling an insulating film in the trench.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: May 8, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Toshiya Nakamori, Hiroshi Kujirai
  • METHOD OF FORMING A SEMICONDUCTOR DEVICE
    Publication number: 20120100702
    Abstract: A method for forming a semiconductor device includes the following processes. A first well including a memory cell region of a semiconductor substrate is formed. A second well including a first peripheral circuit region of the semiconductor substrate is formed after forming the first well.
    Type: Application
    Filed: April 26, 2011
    Publication date: April 26, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Toshiya NAKAMORI
  • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20100022069
    Abstract: An oxide film and a liner film are formed on an inner wall of a trench in a semiconductor substrate. After filling an SOD film in the trench, a heat treatment is carried out. Part of the liner film in contact with the SOD film is removed to expose part of the SOD film. A heat treatment is carried out on the SOD film. An isolating region is formed by filling an insulating film in the trench.
    Type: Application
    Filed: July 2, 2009
    Publication date: January 28, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Toshiya NAKAMORI, Hiroshi Kujirai