Abstract: Clock synchronizing circuitry with a fast tuning circuit has a differentiator for detecting the advanced/delayed state of the phase of an input clock signal and that of an output clock signal. A control amount is changed on the basis of the transition points of the detected phases. Only fast tuning control is executed with usual tuning control masked. Every time a transition point is detected, a selector halves the amount of control. After the control amount has reached .+-.1, the fast tuning control is ended on the detection of the next transition point. Because this kind of control involves a difference between frequency tuning and phase tuning, an integrator calculates a correction amount. One half each control amount is added in the opposite polarity as a correction amount. As a result, fast clock synchronization is achieved.

Abstract: A clock synchronizing circuit includes a voltage controlled oscillator (VCO) for producing an output signal whose oscillation frequency changes in response to control signals. A phase comparator compares a phase of an input signal and a phase of the output signal to thereby generate a phase difference signal. A filter filters the phase difference signal to thereby output a filtered phase difference signal. A frequency synchronizing circuit responsive to the filtered phase difference signal generates a first compensation signal for controlling a frequency of the output signal. A phase synchronizing circuit responsive to the filtered phase difference signal generates a second compensation signal for controlling a phase of the output signal. A signal supplying circuit feeds the first and second compensation signals as the control signals.