Patents by Inventor Toshiya Nozawa

Toshiya Nozawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146140
    Abstract: In this stator, lead wire extended portions and a power wire extended portion are extended from a resin portion by an extended portion separating portion such that the lead wire extended portions are separated from the power wire extended portion by distances that are greater than a maximum value of the width of clearance between an end-side portion of the lead wire extended portion and a facing portion located next to the end-side portion, the resin portion being provided so as to cover lead wire portions and a power wire portion.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 2, 2024
    Applicants: AISIN CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Toshiya SUGIYAMA, Munehiro TAKAHASHI, Keisuke KIMURA, Ken TAKEDA, Takahito NOZAWA, Takashi MATSUMOTO, Yoshitada YAMAGISHI, Katsuhide KITAGAWA, Hajime KATO
  • Publication number: 20180048257
    Abstract: Erroneous mounting of a semiconductor power module can be more easily detected. A semiconductor power module (9) according to the present invention includes: a status signal generation unit (90) configured to detect a status in the semiconductor power module (9) and generate and output a status signal indicating the detected status; an identification information storage unit (91) configured to preliminarily store identification information for identifying the semiconductor power module (9) and output an identification signal indicating the identification information; and a switching unit (92) configured to select one of the status signal output from the status signal generation unit (90) and the identification signal output from the identification information storage unit (91) and output the selected signal to an outside of the semiconductor power module (9).
    Type: Application
    Filed: October 24, 2017
    Publication date: February 15, 2018
    Inventors: Toshiya NOZAWA, Yoshitaro KONDO, Yusuke SUGAWARA, Shoichi KAMIMURA, Masatoshi MAEDA, Yasuhiro SHIRAI
  • Patent number: 9831816
    Abstract: Erroneous mounting of a semiconductor power module can be more easily detected. A semiconductor power module (9) according to the present invention includes: a status signal generation unit (90) configured to detect a status in the semiconductor power module (9) and generate and output a status signal indicating the detected status; an identification information storage unit (91) configured to preliminarily store identification information for identifying the semiconductor power module (9) and output an identification signal indicating the identification information; and a switching unit (92) configured to select one of the status signal output from the status signal generation unit (90) and the identification signal output from the identification information storage unit (91) and output the selected signal to an outside of the semiconductor power module (9).
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: November 28, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiya Nozawa, Yoshitaro Kondo, Yusuke Sugawara, Shoichi Kamimura, Masatoshi Maeda, Yasuhiro Shirai
  • Publication number: 20170093325
    Abstract: Erroneous mounting of a semiconductor power module can be more easily detected. A semiconductor power module (9) according to the present invention includes: a status signal generation unit (90) configured to detect a status in the semiconductor power module (9) and generate and output a status signal indicating the detected status; an identification information storage unit (91) configured to preliminarily store identification information for identifying the semiconductor power module (9) and output an identification signal indicating the identification information; and a switching unit (92) configured to select one of the status signal output from the status signal generation unit (90) and the identification signal output from the identification information storage unit (91) and output the selected signal to an outside of the semiconductor power module (9).
    Type: Application
    Filed: August 9, 2016
    Publication date: March 30, 2017
    Inventors: Toshiya NOZAWA, Yoshitaro KONDO, Yusuke SUGAWARA, Shoichi KAMIMURA, Masatoshi MAEDA, Yasuhiro SHIRAI
  • Patent number: 9331063
    Abstract: A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: May 3, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryo Niide, Shinichi Yamada, Yasuharu Ichinose, Toshiya Nozawa
  • Publication number: 20150249077
    Abstract: A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process.
    Type: Application
    Filed: May 18, 2015
    Publication date: September 3, 2015
    Inventors: Ryo NIIDE, Shinichi YAMADA, Yasuharu ICHINOSE, Toshiya NOZAWA
  • Patent number: 9070614
    Abstract: A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: June 30, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryo Niide, Shinichi Yamada, Yasuharu Ichinose, Toshiya Nozawa
  • Publication number: 20130334562
    Abstract: A semiconductor device simplifies the manufacturing process. The device includes a protective chip which has a surface Zener diode to protect a light emitting chip with an LED formed therein from surge voltage. The protective chip is mounted over a wiring electrically coupled through a metal wire to an anode electrode coupled to a p-type semiconductor region whose conductivity type is the same as that of the semiconductor substrate of the chip. The anode electrode of the protective chip is electrically coupled to the back surface of the chip without PN junction, so even if the back surface is in contact with the wiring, no problem occurs with the electrical characteristics of the Zener diode. This eliminates the need to form an insulating film on the back surface of the chip to prevent contact between the back surface and the wiring, thus simplifying the manufacturing process.
    Type: Application
    Filed: May 23, 2013
    Publication date: December 19, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryo NIIDE, Shinichi YAMADA, Yasuharu ICHINOSE, Toshiya NOZAWA
  • Publication number: 20110115055
    Abstract: To provide a technique that can decrease the leak current due to the photoelectric effect in a semiconductor device with a Zener diode. In a bidirectional Zener diode IZD having a trench structure in the invention, an upper electrode UE extends from an inside of an opening OP to cover a trench TR (isolation region). As shown in FIG. 8, in the bidirectional Zener diode IZD of the invention, the upper electrode UE is formed to cover the inner walls of the trenches TRs. Thus, even when light is applied to the bidirectional Zener diode IZD, the light can be prevented from entering the p-n junction formed at the boundary between the n-type semiconductor region NR and the p-type semiconductor region PR from the inner wall of the trench TR.
    Type: Application
    Filed: November 18, 2010
    Publication date: May 19, 2011
    Inventors: Ryo NIIDE, Toshiya Nozawa
  • Publication number: 20080265373
    Abstract: An epitaxial layer is formed in a main surface of a semiconductor substrate of a first conductivity type. The epitaxial layer is partitioned into a first area and a second area by a device isolation area. A PN junction portion, which has a semiconductor layer of a second conductivity type and configures a variable capacitance element, is provided at the surface of the epitaxial layer of the first area. A PN junction portion, which has a semiconductor layer of the second conductivity type whose low portion is formed closer to the semiconductor substrate than the semiconductor layer of the second conductivity type configuring the above variable capacitive PN junction and which is configured as a fixed capacitance, is provided at the surface of the epitaxial layer of the second area.
    Type: Application
    Filed: April 22, 2008
    Publication date: October 30, 2008
    Inventors: Toshiya Nozawa, Ryo Niide, Itaru Iijima
  • Patent number: 7372159
    Abstract: A glass-sealed type semiconductor device has Dumet electrodes, a glass sealing member, and a semiconductor element tightly sealed in a cavity constituted by the Dumet electrodes and the glass sealing member. The semiconductor element is constituted by a Schottky barrier diode. External leads serving as external terminals of the semiconductor device are connected to the Dumet electrodes, respectively. The Dumet electrodes have core portions comprised of a nickel-iron alloy, copper layer formed on the outer peripheries of the core portions, and copper oxide layers formed on the outer surfaces of the copper layers, respectively. The ratios of the copper layers are 20 wt % or more each.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: May 13, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Toshiya Nozawa, Masahito Mitsui
  • Publication number: 20040188847
    Abstract: A glass-sealed type semiconductor device has Dumet electrodes, a glass sealing member, and a semiconductor element tightly sealed in a cavity constituted by the Dumet electrodes and the glass sealing member. The semiconductor element is constituted by a Schottky barrier diode. External leads serving as external terminals of the semiconductor device are connected to the Dumet electrodes, respectively. The Dumet electrodes have core portions comprised of a nickel-iron alloy, copper layer formed on the outer peripheries of the core portions, and copper oxide layers formed on the outer surfaces of the copper layers, respectively. The ratios of the copper layers are 20 wt % or more each.
    Type: Application
    Filed: March 30, 2004
    Publication date: September 30, 2004
    Inventors: Toshiya Nozawa, Masahito Mitsui