Abstract: A data driven type information processor includes a program storing unit, a junction unit, a paired data detecting unit, a branch unit and an operation processing unit. The program storing unit has a program memory divided into N regions in each of which a data flow program which is previously divided is stored. In operation, the program storing unit individually and simultaneously addresses each of the N regions based on destination information in an applied data packet to collectively read program data from the respective regions. The read N program data are sequentially applied to the operation processing unit through the junction unit, the paired data detecting unit and the branch unit.

Abstract: A data pair detecting portion of a data flow type information processor outputs a data packet including a destination field and an instruction field and a data packet including two data fields. The data packet including the destination field and the instruction field is separated into a data packet including the destination filed and a data packet including the instruction field. The data packet including the destination field is applied to a program storing portion and the data packet including the instruction field is applied to an operation processing portion. The data packet including the two data fields is also applied to the operation processing portion. In a copy processing or in a constant reading processing, the program storing portion outputs a further data packet including a destination field and an instruction field or a data packet including a constant simultaneously with a data packet including a destination field and an instruction field.

Abstract: A data driven type information processor includes a program storing unit storing a data flow program in a number of memory banks wherein the number is greater than one. The data flow program includes a series of program lines divided into a plurality of clusters, and the memory banks store the data flow program such that each program line of a cluster is stored in a different memory bank. Each program line includes at least destination information and instruction information, and the destination information includes at least a cluster identifier. The program storing unit responsive to a cluster identifier of received destination information reads a cluster of program lines stored in the memory banks. The program storing unit outputs an instruction data packet corresponding to each read program line wherein the instruction data packet includes destination information and instruction information.

Abstract: A system of loading and dumping data in an information processor includes a program control portion, a paired data detecting portion and an operation processing portion. An execution packet applied to the program control portion has a destination information field showing the destination of the execution packet, an identifier field for identifying data having the queue address of the paired data detecting portion, and an address information field for identifying paired data, together with the identifier, in the paired data detecting portion and for informing the program control portion of the next instruction to be fetched. The identifier field is used as a part of an address for sending data and a number for identifying the information processor. The number is contained in a part of the queue address so that a structure of the packet is converted and the packet after conversion is used for loading and dumping data.

Abstract: A data flow type information processor includes first and second program storing portions, a merging portion, a data pair detecting portion and first and second operation processing portions. Each of the first and the second program storing portions stores a data flow program and outputs a data packet including destination information and instruction information read from the data flow program based on an input data packet. The merging portion performs arbitration between data packets output from said first and second program storing portions. The data pair detecting portion receives a data packet output from the merging portion to detect two data packets having the same destination information.

Abstract: A parallel processor developing system comprises a control computer, an interface portion, a processing element, a tracer portion and a display portion. The processing element comprises a data driven type processor. The interface portion stores data packets supplied from the control computer and applies the data packets to the processing element at a predetermined time interval. The tracer portion stores the data packets supplied from predetermined ports of the processing element together with time information. The display portion displays storage contents of the tracer portion.

Abstract: A data flow type information processor includes a program storing portion, a paired data detecting portion, an operation processing portion, an internal data buffer, and an external data memory. A data packet processed in the program storing portion, the paired data detecting portion and the operation processing portion is transferred to the internal data buffer. On the other hand, a data packet outputted from the external data memory is transferred to another information processor through a merge portion, a branch portion, another merge portion and another branch portion. Thus, internal processing through the internal data buffer and processing from the external data memory to the exterior are not merged.

Abstract: An information processor includes a program memory for storing a data flow program having destination information and instruction information as one set. Destination information, instruction information and operand data included in an input data packet are latched in an input data latching portion. Only the operand data is transferred to an output data latching portion. An address is operated based on the destination information latched in the input data latching portion, and the program memory is accessed, so that the data flow program is read out. The destination information and the instruction information included in the read data flow program are latched in the output data latching portion. Paired data is detected by a paired data detection portion based on the data flow program latched in the output data latching portion. The detected data is operated by an operation processing portion.

Abstract: An apparatus for debugging a data flow program simulates functions corresponding to a plurality of structural portions of a processing apparatus in accordance with a data flow program stored in a program file. The state of execution corresponding to respective lines of a source program of the executed plurality of functional portions are stored in a PS file and the processes in respective functional portions and the states of execution employed for the execution of the source program are stored in a data packet file. A debug information file (22) stores the debug information indicative of the corresponding relation between the respective lines of the source program and respective nodes of the data flow program. A display displays debug information in association with respective lines of the source program in accordance with the execution of respective nodes of the data flow program.

Abstract: A simulation method and a computer therefor, i.e., a simulator, for simulating operation of a circuit employing logic gates. The simulation method is to be called the event drive method, in which the output processing is executed only when an input to cause output changes and the output level and the start and finish time for the level are sent out. Hence the number of packets of data flowing for simulation can be minimized and also the number of times of data processing is reduced. This system is applied to each component in a logic circuit, whereby the parallel execution of processing as to the parallel components is possible so as to devise the simulation at a higher speed.