Abstract: A wireless communication device includes: a master terminal that includes an antenna element, an RF circuit, a control unit, and a MIMO processing unit connected with the RF circuit; and a slave terminal that includes an antenna element and an RF circuit. The slave terminal is connected with the master terminal via an interface that includes a high-frequency transmission path. The control unit can control the MIMO processing unit and each RF circuit, and controls the MIMO processing unit to perform a MIMO reception process based on an RF signal that is received by the master terminal and an RF signal that is received by the slave terminal and transmitted to the master terminal.

Abstract: A wireless communication device with MIMO function conforming to a predetermined wireless standard and communication terminals that communicate with a base station incorporating MIMO function includes a master communication terminal which is any one of the plurality of communication terminals and a slave communication terminal which is connected to the master communication terminal via a predetermined connection element and is one or more communication terminals other than the master communication terminal among the plurality of communication terminals. A configuration in which a part of or all signal processing functions that relate to transmission and reception of one or more antennas incorporated in one or more slave communication terminals can be controlled from the master communication terminal is used.

Abstract: A wireless communication device includes: a master terminal that includes an antenna element, an RF circuit, a control unit, and a MIMO processing unit connected with the RF circuit; and a slave terminal that includes an antenna element and an RF circuit. The slave terminal is connected with the master terminal via an interface that includes a high-frequency transmission path. The control unit can control the MIMO processing unit and each RF circuit, and controls the MIMO processing unit to perform a MIMO reception process based on an RF signal that is received by the master terminal and an RF signal that is received by the slave terminal and transmitted to the master terminal.

Abstract: A wireless communication device with MIMO function conforming to a predetermined wireless standard and communication terminals that communicate with a base station incorporating MIMO function includes a master communication terminal which is any one of the plurality of communication terminals and a slave communication terminal which is connected to the master communication terminal via a predetermined connection element and is one or more communication terminals other than the master communication terminal among the plurality of communication terminals. A configuration in which a part of or all signal processing functions that relate to transmission and reception of one or more antennas incorporated in one or more slave communication terminals can be controlled from the master communication terminal is used.

Abstract: A data error correction system, which is capable of executing repeated error correction processing, and which improves the quality of communication links by allowing repeated corrections of errors generated in the transmission line, comprises a Viterbi decoder for decoding a designated encoded data from a buffer and a block decoder for executing decoding of the data corresponding to a length of a block code after being decoded from the Viterbi decoder, when error correction is possible. The data error correction system controls execution of re-decoding by the Viterbi decoder for executing error correction of the data corresponding to a length of a block code whose correction has not been possible yet.

Abstract: By using a branch metric and a path metric which are produced from received data every symbol time, an ACS circuit 13 produces a path-selecting information while renewing the path metric by adding the branch metric entering the state to path metric of the connecting survivor for all the paths entering a state in accordance with Viterbi algorithm. The path-selecting information is sequentially stored in each of path memory blocks. The path memory blocks are connected to one another so that a result of the trace-back may become a starting point for starting the trace-back of a next path memory block when trace-back is made. The trace-back is started from a selected one of the path memory blocks having a state number obtained by a maximum path state number detector. An output of the selected path memory block is output via a selector as decoded data.

Abstract: A Viterbi decoding apparatus decoding packet data, even at the case that next packet data are continuously inputted soon after the existing packet data, can correctly decode the last part of the existing packet data is provided. The Viterbi decoding apparatus provides a selector that switches a receiving clock synchronized with the packet data and a high speed clock being faster than the receiving clock. During the packet data are received, the selector supplies the receiving clock to a branch metric generator, an ACS (add, compare and select) circuit, a path metric register, a path memory and a trace back circuit. After the reception of the packet data is finished, the selector supplies the high speed clock to the branch metric generator, the ACS circuit, the path metric register and the path memory. With this, the Viterbi decoding apparatus of the present invention can decode the last part of the existing packet data correctly and quickly.

Abstract: In time diversity communication system, loss of data or generation of incorrect data may occur due to, for example, the shadow effect. In the present invention, on the transmission side, an interlaced signal is generated in which the input digital signal string is combined with the same signal string delayed by n bits, k redundancy bits are added to every m bits of this signal, the signal is divided into blocks of (m+k) bits, an interleaving process is executed for every j blocks in which unique words are added, following which the signal is transmitted. On the receiving side, unique words are detected, a de-interleaving process is performed, and a check is made for the presence of error signals. The delayed and non-delayed signals are next separated from the decoded data, and depending on the state of the signals, the desired signal is selected at selector 33 and outputted.

Abstract: A branch value output circuit checks a preceding state to which a maximum path metric state determined in a Viterbi decoding process by a Viterbi decoder has transited, uses the maximum path metric state, and determines a branch value between transitions. A correlator determines a correlation in each interval between the branch value and soft-decided received data and outputs a correlative value representing the correlation in each interval. A synchronism/asynchronism determining circuit determines whether the received data are in a synchronous or asynchronous condition based on the correlative value in each interval. If the received data are determined to be in an asynchronous condition by the synchronism/asynchronism determining circuit, the synchronism/asynchronism determining circuit supplies a phase control signal to a phase converter. The phase converter changes the phase of the received data in response to the phase control signal.

Abstract: A Viterbi decoder includes a branch metric generator, a subset maximum likelihood estimator, an accumulator switch circuit (ACS circuit), a most likely path setter, a first selector, and a path-memory circuit for the purpose of estimating encoding bits of a 4-bit error-correcting encoded information symbol string. The Viterbi decoder also includes a noncoding bit detector, eight j-level shift registers, and a second selector for the purpose of estimating a noncoding bit of the 4-bit error-correcting encoded information symbol string. The j-level shift registers are provided for temporarily holding the output signals of the noncoding bit detector. The second selector is provided for selecting one output signal from the output signals of the j-level shift registers in accordance with the output signal of the selector.

Abstract: A Viterbi decoder includes a first inverse mapping circuit, first to fourth branch metric generators, first to eighth accumulator switch circuits (ACS circuits) with one ACS circuit corresponding to one of the eight states of the feedback-type convolutional encoder, a path memory, and a re-encoder for the purpose of decoding an influential bit and a redundant bit of 4-bit error-correcting encoded information symbol string from I-channel data and Q-channel data. A Viterbi decoder also includes first and second shift registers having a number of levels determined according to the delay in the re-encoder and the delay in the path memory and a second inverse mapping circuit for the purpose of decoding noncoding bits of 4-bit error-correcting encoded information symbol string using the I-channel data and the Q-channel data.

Abstract: An error-correcting tandem encoding system includes a transmitter section and a receiver section. The transmitter section comprises a multiplexer for multiplexing data and voice signals supplied thereto, a Reed-Solomon encoder for Reed-Solomon-encoding an output signal from the multiplexer while interleaving the output signal without causing a delay, a convolutional encoder for convolutionally encoding a Reed-Solomon encoded signal from the Reed-Solomon encoder, and a PSK modulator having a fixed bit rate for phase-shift-keying an output signal from the convolutional encoder.

Abstract: A data transmission system for transmitting data by way of encoding modulation has a transmitter including a convolutional encoder and a receiver including a Viterbi decoder. For the case when the bit rate is changed, the data transmission system employs the same modulator/demodulator, and effectively utilizes a frequency band which is unchanged. The transmitter includes a selector for periodically switching two output signals, one having a redundant bit produced from the convolutional encoder and the other having an information bit instead of a redundant bit, resulting in a variable encoding ratio. The Viterbi decoder decodes a designated signal from the convolutional encoder. The receiver also includes a circuit for reconstructing branch metrics only when a received symbol composed of only an information bit without a redundant bit is supplied, and circuits for regenerating a information bit which is added without depending on the encoding.

Abstract: In a serial input-output circuit comprising a memory device (15) for memorizing an input serial bit sequence as memorized bit groups, each consisting of a predetermined number of parallel bits, first and second bidirectional shift registers (21, 22) are serially connected through a ring connection (24, 25). A storing arrangement (35-37) is connected to the respective shift registers and directly to the memory device for bit parallel storage of the parallel bits of a selected one of the memorized bit groups in a selected one of the shift registers. An output serial bit sequence is produced from one of the shift registers selectively forwardly and backwardly as regards time relative to the input serial bit sequence. The storing arrangement may comprise a register selector (35) and first and second bit parallel connections (36, 37).

Abstract: A carrier-to-noise detector comprises an A/D converter (1) which samples an output of the demodulator of a digital transmission system at a symbol clock rate and converting it to a digital signal having positive and negative values. An absolute value converting circuit (2) converts the output of A/D converter into an absolute value which is averaged by a first averaging circuit (3) over a period sufficient to suppress short term variations and then squared by a first squaring circuit (4) to give an output representing the carrier component. The output of A/D converter is, on the other hand, squared by a second squaring circuit (5) and averaged by a second averaging circuit (6) to suppress short term variations to give an output representing a total of the carrier and noise components. The carrier component in the output of the second averaging circuit 6 is subtracted by a subtractor (7).