Patents by Inventor Toshiya Toyoshima

Toshiya Toyoshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6413791
    Abstract: An epitaxial semiconductor crystal plate or wafer capable of attaining increased reliability with enhanced luminance, a manufacturing method thereof, as well as a light-emitting diode (LED). It has been found that epitaxial wafers with enhanced illuminance and increased yield of manufacture can be fabricated by specifically arranging a double-heterostructure epitaxial wafer such that the interface between its p-type clad layer 2 and p-type GaAlAs active layer 3 and that between an n-type GaAlAs clad layer 4 and p-type GaAlAs active layer 3 measure 1×1017 cm−3 or less in oxygen concentration. Also, in order to cause the oxygen concentration near the p-type GaAlAs active layer 3 in layers of the epitaxial wafer to be less than or equal to 1×1017 cm−3, it may be preferable that a nondoped GaAs polycrystal for use as a preselected original material in liquid-phase epitaxial growth be less than or equal to 1×1016 cm−3 or there about.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: July 2, 2002
    Assignee: Hitachi Cable Ltd.
    Inventors: Yukiya Shibata, Seiji Mizuniwa, Toshiya Toyoshima
  • Patent number: 6043509
    Abstract: A Light-emitting diode having improved moisture resistance characteristics comprises a p-type gallium arsenide substrate and four epitaxial layers of Al.sub.x Ga.sub.1-x As (22, 23, 24 and 25). These epitaxial layers comprises an intervening layer (22) of p-type Al.sub.x1 Ga.sub.1-x1 As, a cladding layer (23) of p-type Al.sub.x2 Ga.sub.1-x2 As, an active layer (24) of Al.sub.x3 Ga.sub.1-x3 As, and a window layer (25) of Al.sub.x4 Ga.sub.1-x4 As so as to form a double-hetero structure, where x1, x2, x3 and x4 represent mixed crystal ratios of aluminum to arsenic of the layers, respectively, and meet the condition that:x2.gtoreq.x4>x1.gtoreq.x3 (0.ltoreq.x1, x2, x3, x4.ltoreq.1).
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: March 28, 2000
    Assignee: Hitachi Cable, Ltd.
    Inventors: Tooru Kurihara, Toshiya Toyoshima, Seiji Mizuniwa, Masahiro Noguchi
  • Patent number: 5965908
    Abstract: An epitaxial semiconductor crystal plate or wafer capable of attaining increased reliability with enhanced luminance, a manufacturing method thereof as well as a light-emitting diode (LED). It has been found that epitaxial wafers with enhanced illuminance and increased yield of manufacture can be fabricated by specifically arranging a double-heterostructure epitaxial wafer such that the interface between its p-type clad layer 2 and p-type GaAlAs active layer 3 and that between an n-type GaAlAs clad layer 4 and p-type GaAlAs active layer 3 measure 1.times.10.sup.17 cm.sup.-3 or less in oxygen concentration. Also, in order to cause the oxygen concentration near the p-type GaAlAs active layer 3 in layers of the epitaxial wafer to be less than or equal to 1.times.10.sup.17 cm.sup.-3, it may be preferable that a nondoped GaAs polycrystal for use as a preselected original material in liquid-phase epitaxial growth be less than or equal to 1.times.10.sup.16 cm.sup.-3 or thereabout.
    Type: Grant
    Filed: December 15, 1997
    Date of Patent: October 12, 1999
    Assignee: Hitach Cabel, Ltd.
    Inventors: Yukiya Shibata, Seiji Mizuniwa, Toshiya Toyoshima
  • Patent number: 5888843
    Abstract: A light-emitting diode having improved moisture resistance characteristics comprises a p-type gallium arsenide substrate and four epitaxial layers of Al.sub.x Ga.sub.1-x As (22, 23, 24 and 25). These epitaxial layers comprises an intervening layer (22) of p-type Al.sub.x Ga.sub.1-x As, a cladding layer (23) of p-type Al.sub.x2 Ga.sub.1-x2 As, an active layer (24) of Al.sub.x3 Ga.sub.1-x3 As, and a window layer (25) of Al.sub.x4 Ga.sub.1-x4 As so as to form a double-hetero structure, where x1, x2, x3 and x4 represent mixed crystal ratios of aluminum to arsenic of the layers, respectively, and meet the condition that:x2.gtoreq.x4>x1.gtoreq.x3 (0.ltoreq.x1, x2, x3, x4.ltoreq.1).
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: March 30, 1999
    Assignee: Hitachi Cable, Ltd.
    Inventors: Tooru Kurihara, Toshiya Toyoshima, Seiji Mizuniwa, Masahiro Noguchi
  • Patent number: 4483735
    Abstract: The present invention relates to the manufacturing process of semi-insulating gallium arsenide single crystal by pulling a seed crystal contacted with gallium arsenide melt which is obtained by heat-reacting gallium and arsenic in a crucible contained in a pressure container and is characteristic in providing a film layer of 8-20 mm thickness of melted boron oxide with less than 200 ppm water content under pressure controlled at 60 kg/cm.sup.2 and over during reaction and at 5-40 kg/cm.sup.2 during crystal growth in high purity inert gas atmosphere, and during said crystal growth, rotating said seed crystal and said crucible in the same direction, but said seed crystal being rotated 5-30 rpm faster than the said crucible, and setting the crystal growing plane of said seed crystal to be within .+-.3.degree. from {100} plane.
    Type: Grant
    Filed: March 11, 1983
    Date of Patent: November 20, 1984
    Assignee: Hitachi Cable, Ltd.
    Inventors: Tomoki Inada, Seiji Mizuniwa, Toshiya Toyoshima, Masashi Fukumoto, Junkichi Nakagawa