Abstract: The temperature dependence of detection characteristics in a wave detector circuit is suppressed. A bias resistor and/or a load resistor are/is constituted by a resistive element having a high temperature coefficient, whereby a shift in detected output along with a change in temperature of a wave detector diode included in a diode detector circuit is canceled by a shift in detected output along with a change in temperature of the bias resistor and/or a shift in detected output along with a change in temperature of the load resistor.

Abstract: The temperature dependence of detection characteristics in a wave detector circuit is suppressed. A bias resistor and/or a load resistor are/is constituted by a resistive element having a high temperature coefficient, whereby a shift in detected output along with a change in temperature of a wave detector diode included in a diode detector circuit is canceled by a shift in detected output along with a change in temperature of the bias resistor and/or a shift in detected output along with a change in temperature of the load resistor.

Abstract: The temperature dependence of detection characteristics in a wave detector circuit is suppressed. A bias resistor and/or a load resistor are/is constituted by a resistive element having a high temperature coefficient, whereby a shift in detected output along with a change in temperature of a wave detector diode included in a diode detector circuit is canceled by a shift in detected output along with a change in temperature of the bias resistor and/or a shift in detected output along with a change in temperature of the load resistor.

Abstract: In order to lay out a power amplifier heterojunction bipolar transistor capable of large power output in a small area, the subject invention provides a heterojunction bipolar transistor constituted of a plurality of transistor components arranged on a sub-collector layer, collector layers of said transistor components being separated one another, said transistor components being arranged in a line in a longitudinal direction of an emitter. The subject invention also provides a multi-finger type heterojunction bipolar transistor using the heterojunction bipolar transistor as a unit transistor.

Abstract: A Pt alloyed reaction layer is formed under a base ohmic electrode. This alloyed reaction layer extends through a base protective layer so as to reach a base layer. Besides, a Pt alloyed reaction layer is formed under an emitter ohmic electrode. This alloyed reaction layer is formed only within a second emitter contact layer. With this constitution, the manufacturing cost for the HBT can be reduced and successful contact characteristics for the HBT can be obtained.

Abstract: A Pt alloyed reaction layer is formed under a base ohmic electrode. This alloyed reaction layer extends through a base protective layer so as to reach a base layer. Besides, a Pt alloyed reaction layer is formed under an emitter ohmic electrode. This alloyed reaction layer is formed only within a second emitter contact layer. With this constitution, the manufacturing cost for the HBT can be reduced and successful contact characteristics for the HBT can be obtained.

Abstract: An inverter portion, which is to be basic logic circuit, includes switching FETs corresponding to input terminals and a load FET. A logic signal inputted into each of the input terminals drives each corresponding switching FET, thereby to output a prescribed logic signal from an output terminal. Further, a load for restricting a current flowing in the load FET is connected between the gate and the source of the load FET. In addition, a load current control FET is provided for controlling the current in this load. A gate potential of the load current control FET is produced by a diode OR circuit. The diode OR circuit outputs a logic OR of the logic signals inputted into the respective input terminals, and supplies it to the gate of the load current control FET as a load current control signal.