Patents by Inventor Toshiyasu Morita
Toshiyasu Morita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250070172Abstract: An anthraquinone-based active material for a redox flow battery includes a first compound represented by the following chemical formula: where at least one of the R1 to R8 is a hydroxy group, and at least one of the R1 to R8 is an alkoxy group.Type: ApplicationFiled: December 19, 2022Publication date: February 27, 2025Applicants: MITSUBISHI HEAVY INDUSTRIES, LTD., NAGOYA DENKI EDUCATIONAL FOUNDATIONInventors: Koichiro Hirayama, Toshiyasu Kiyabu, Yasushi Morita, Tsuyoshi Murata, Aya Ito, Shigemitsu Okada
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Publication number: 20250059125Abstract: A method of producing an anthraquinone-based substance represented by the following chemical formula: where at least one of R1 to R8 is a hydroxy group, and at least one of R1 to R8 is an alkoxy group, includes the steps of: preparing a starting material represented by the following chemical formula: where at least two of the R1? to R8? are hydroxy groups; and reacting the starting material with an organic alkylating agent. The amount of the organic alkylating agent to be reacted with the starting material is more than or equal to 0.05 mol and less than n mol per 1 mol of the starting material, where n is the number of hydroxy groups contained in the starting material.Type: ApplicationFiled: December 19, 2022Publication date: February 20, 2025Applicants: MITSUBISHI HEAVY INDUSTRIES, LTD., NAGOYA DENKI EDUCATIONAL FOUNDATIONInventors: Koichiro Hirayama, Toshiyasu Kiyabu, Yasushi Morita, Tsuyoshi Murata, Aya Ito, Shigemitsu Okada
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Patent number: 7877572Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.Type: GrantFiled: August 6, 2008Date of Patent: January 25, 2011Assignee: Renesas Technology America, Inc.Inventors: Toshiyasu Morita, Shumpei Kawasaki
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Publication number: 20080313383Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.Type: ApplicationFiled: August 6, 2008Publication date: December 18, 2008Applicant: Renesas Technology America, Inc.Inventors: Toshiyasu Morita, Shumpei Kawasaki
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Patent number: 7412581Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.Type: GrantFiled: October 28, 2003Date of Patent: August 12, 2008Assignee: Renesas Technology America, Inc.Inventors: Toshiyasu Morita, Shumpei Kawasaki
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Publication number: 20050091468Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.Type: ApplicationFiled: October 28, 2003Publication date: April 28, 2005Applicant: Renesas Technology America, Inc.Inventors: Toshiyasu Morita, Shumpei Kawasaki
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Patent number: 6845908Abstract: A storage card includes non-volatile memory; an authentication engine capable to authenticate a password and transmit authorization to read from and write to files; a file system, coupled to the authentication engine, capable to receive file commands from a computer, receive authorization from the authentication engine, and to transmit file instructions; and a sector driver, coupled to the file system and the memory, capable to read from and write to the memory in response to the instructions received from the file system.Type: GrantFiled: March 18, 2002Date of Patent: January 25, 2005Assignee: Hitachi Semiconductor (America) Inc.Inventors: Toshiyasu Morita, Shumpei Kawasaki
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Publication number: 20030173400Abstract: A storage card includes non-volatile memory; an authentication engine capable to authenticate a password and transmit authorization to read from and write to files; a file system, coupled to the authentication engine, capable to receive file commands from a computer, receive authorization from the authentication engine, and to transmit file instructions; and a sector driver, coupled to the file system and the memory, capable to read from and write to the memory in response to the instructions received from the file system.Type: ApplicationFiled: March 18, 2002Publication date: September 18, 2003Applicant: Hitachi Semiconductor (America) Inc.Inventors: Toshiyasu Morita, Shumpei Kawasaki
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Publication number: 20030177342Abstract: The processor has a set of registers with each register having a dirty bit. The processor executes a method comprising: determining if a register used by a first function has a set dirty bit; and if the dirty bit is set: pushing data from the register to a stack; clearing the dirty bit; storing a bitmask in the stack indicating the register from which data was pushed; and restoring data to the register from the stack after execution of a second function that used the register.Type: ApplicationFiled: March 15, 2002Publication date: September 18, 2003Applicant: Hitachi Semiconductor (America) Inc.Inventor: Toshiyasu Morita
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Patent number: 6275984Abstract: A system and method for delaying indirect register offset resolution including a processor having a plurality of registers, a memory storing program instructions, and a compiler for translating the program instructions into executable object code for execution by the processor. In addition, the invention includes a set of offset register lists for storing offset values generated by the compiler.Type: GrantFiled: November 20, 1998Date of Patent: August 14, 2001Assignee: Sega of America, Inc.Inventor: Toshiyasu Morita
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Patent number: 6155923Abstract: Videogame systems and methods are provided to enhance the capability of the videogame system controller and data storage to provide graphic character element storage and processing. A display list technology utilizes an intentionally generated, location-specific vertical interrupt to implement a routine to modify or to alter existing graphical character elements. A second technique involves the definition of a small portion of the graphics map which is displayed differently than the balance of the graphics map because the stored priority bit is expressed in the defined area, but suppressed and replaced in all other areas. The third technique employs a virtual character element library to map the character elements appearing on the display, and recognizes available space within the video random access memory character element storage to provide a dynamic memory space.Type: GrantFiled: December 6, 1996Date of Patent: December 5, 2000Assignee: Sega Enterprises, Ltd.Inventors: Adrian Stephens, Toshiyasu Morita
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Patent number: 5935003Abstract: Videogame systems and methods are provided to enhance the capability of the videogame system controller and data storage to provide graphic character element storage and processing. A display list technology utilizes an intentionally generated, location-specific vertical interrupt to implement a routine to modify or to alter existing graphical character elements. A second technique involves the definition of a small portion of the graphics map which is displayed differently than the balance of the graphics map because the stored priority bit is expressed in the defined area, but suppressed and replaced in all other areas. The third technique employs a virtual character element library to map the character elements appearing on the display, and recognizes available space within the video random access memory character element storage to provide a dynamic memory space.Type: GrantFiled: December 6, 1996Date of Patent: August 10, 1999Assignee: Sega of America, Inc.Inventors: Adrian Stephens, Toshiyasu Morita