Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.

Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.

Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.

Abstract: Apparatus and method are described for a data processing device. The data processor includes features suitable for executing a software virtual machine. The data processor provides an instruction set that supports object-level memory protection suitable for high speed operation. Memory control logic is provided to accommodate a configuration having relatively less random access memory (RAM) as compared to re-programmable, nonvolatile memory, and to improve access to the re-programmable, nonvolatile memory.

Abstract: A storage card includes non-volatile memory; an authentication engine capable to authenticate a password and transmit authorization to read from and write to files; a file system, coupled to the authentication engine, capable to receive file commands from a computer, receive authorization from the authentication engine, and to transmit file instructions; and a sector driver, coupled to the file system and the memory, capable to read from and write to the memory in response to the instructions received from the file system.

Abstract: The processor has a set of registers with each register having a dirty bit. The processor executes a method comprising: determining if a register used by a first function has a set dirty bit; and if the dirty bit is set: pushing data from the register to a stack; clearing the dirty bit; storing a bitmask in the stack indicating the register from which data was pushed; and restoring data to the register from the stack after execution of a second function that used the register.

Abstract: A storage card includes non-volatile memory; an authentication engine capable to authenticate a password and transmit authorization to read from and write to files; a file system, coupled to the authentication engine, capable to receive file commands from a computer, receive authorization from the authentication engine, and to transmit file instructions; and a sector driver, coupled to the file system and the memory, capable to read from and write to the memory in response to the instructions received from the file system.

Abstract: A system and method for delaying indirect register offset resolution including a processor having a plurality of registers, a memory storing program instructions, and a compiler for translating the program instructions into executable object code for execution by the processor. In addition, the invention includes a set of offset register lists for storing offset values generated by the compiler.

Abstract: Videogame systems and methods are provided to enhance the capability of the videogame system controller and data storage to provide graphic character element storage and processing. A display list technology utilizes an intentionally generated, location-specific vertical interrupt to implement a routine to modify or to alter existing graphical character elements. A second technique involves the definition of a small portion of the graphics map which is displayed differently than the balance of the graphics map because the stored priority bit is expressed in the defined area, but suppressed and replaced in all other areas. The third technique employs a virtual character element library to map the character elements appearing on the display, and recognizes available space within the video random access memory character element storage to provide a dynamic memory space.

Abstract: Videogame systems and methods are provided to enhance the capability of the videogame system controller and data storage to provide graphic character element storage and processing. A display list technology utilizes an intentionally generated, location-specific vertical interrupt to implement a routine to modify or to alter existing graphical character elements. A second technique involves the definition of a small portion of the graphics map which is displayed differently than the balance of the graphics map because the stored priority bit is expressed in the defined area, but suppressed and replaced in all other areas. The third technique employs a virtual character element library to map the character elements appearing on the display, and recognizes available space within the video random access memory character element storage to provide a dynamic memory space.