Abstract: A wiring design device to conduct wiring design on a printed wiring board that includes a plurality of conductive layers, the wiring design device including: noise contaminating part extracting means for extracting a part in a condition where noise contaminates a signal, the part being on a wiring-designed line, based on a route of the line and a physical condition around the route; route modification processing means for modifying the route of the line by moving the extracted part on the line in the condition where noise contaminates the signal to a position that avoids the condition where noise contaminates the signal; and line length adjusting means for conducting a line length adjustment on the line to compensate for a variation of the line length of the line when the variation of the line length of the line occurs due to modifying the route of the line.

Abstract: A computer-readable, non-transitory medium stores therein a design support program that causes a computer executing tentative wiring processing between a first terminal group and a second terminal group in a tentative wiring area to execute a process. The process includes detecting unwired nets occurring in the tentative wiring area consequent to the tentative wiring processing; updating the tentative wiring area by expanding the tentative wiring area according to the number of unwired nets, if any unwired nets are detected at the detecting; controlling to execute the tentative wiring processing and the subsequent detecting with respect to the tentative wiring area updated at the updating; and determining the tentative wiring area to be a wiring area if no unwired nets are detected at the detecting.

Abstract: A printed circuit board design assisting method, device and storage medium are provided. The assisting method includes referring to the position of terminals of a grid array package part, and attributes indicating whether each of the terminals is a power source terminal or a ground terminal, and selecting the power source terminals as a terminal to be researched, searching for a new connection path between the terminal which has been selected, and one of the ground terminals, by way of a first decoupling capacitor, determining whether there is duplication of paths between the new connection path and an connection path between the terminals connected by way of a second decoupling capacitor, changing the position of the second decoupling capacitor if duplication is detected, and re-searching a connection path between the terminals by way of the second decoupling capacitor, which is not in duplicate with the new connection path.

Abstract: A wiring design apparatus for designing a plurality of wiring lines of a printed circuit board including a plurality of connection posts arranged in a matrix, includes a processor, the processor providing an orthogonal grid including a plurality of rows and columns running over and between the connection posts, providing a plurality of diagonal paths each connecting at least one of the rows with at least one of the columns each running between each of adjacent pairs of the connection posts, and determining a route for each of the wiring lines by exclusively allocating to each of the wiring lines a selected part of the rows, the columns and the paths so that the selected part connects both ends of each of the wiring lines.

Abstract: When a formed position of a via formed on a board is the same as a position of a footprint of a chip component located on the back surface of the board corresponding to an area on which a BGA is mounted, a board designing apparatus determines that the chip component and the BGA can be connected using chip on hole. When it is determined that the chip component and the BGA can be connected, the board designing apparatus carries out chip on hole by forming a via in an area of the board on which the BGA is mounted, the via leading to the footprint of the chip component located on the back surface of the board.

Abstract: A wiring design apparatus includes a first acquirer that acquires a first wiring block whose region has a maximum number of crossings with regions of other wiring blocks from printed circuit board data of a printed circuit board having a plurality of wiring blocks with a specific region on a wiring layer, a second acquirer that acquires second wiring blocks whose region does not cross the first wiring block from the printed circuit board data, and a wiring execution requester that causes a wiring processor to perform wiring processing on the first wiring block and the second wiring blocks in parallel.

Abstract: An automatic routing method and an automatic routing apparatus enable an optimum automatic routing under severe design conditions due to high-density mounting of an object of a wiring design such as an LSI, a multichip module, a printed wiring board, etc. The automatic routing apparatus has an area input unit for inputting area information for setting a routing controlled area in which an automatic routing is performed under specific routing control conditions within a wiring area of an object of the wiring design, a condition input unit for inputting condition information for designating the routing control conditions in the routing controlled area set according to the area information inputted from the area input unit, and an automatic routing unit for automatically routing under the specific routing control conditions designated according to the condition information inputted from the condition input unit within the routing controlled area.

Abstract: A routing preprocessing unit properly rearranges routing conditions beforehand with respect to parts in which physical conditions in terms of assembling or packaging in an original circuit are changeable. A feedback section feeds pin assignment data back to an assembling or a packaging design system for high-order hierarchy parts in the original circuit and thus changes a pin assignment through a design of the high-order hierarchy parts themselves. An automatic routing unit specifically designs high-density wiring patterns without using a via. A routing layer allocating section collects part-to-part route bundles bearing such a positional relationship as to cause no intersection and no overlap on the basis of routing data and allocates the route bundle to the same routing layer on a multilayer routing board including a plurality of routing layers. A routing order determining section determines a routing order of the route bundle.

Abstract: This invention is directed to a method and apparatus to find out an optimum solution in automatic routing or automatic placement with certainty and at a high-speed to improve a routing rate, and to realize automatic routing in a high-density. To these end, a routing approach is selected in a conversational mode while routing efficiency is consulted to compose routing processing procedure so as to generate a routing program. Besides, component placement processing procedures designated according to placement control information are combined to generate the placement program. A straight line between component pins adjacent to each other is defined as a chord, a wave for maze method routing is generated from a start point toward an end point of a routing path and propagated between the chords adjacent to each other.